Simulation Results: spi_host

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.30 %
  • code
  • 95.02 %
  • assert
  • 93.54 %
  • func
  • 88.33 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 11.000s 2263.642us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 42.318us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 17.586us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 338.149us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 37.006us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 549.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 17.586us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.006us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 17.053us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 26.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 59.662us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 598.132us 1 1 100.00
spi_host_error_cmd 1.000s 27.368us 1 1 100.00
spi_host_event 25.000s 3599.355us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 108.971us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 108.971us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 108.971us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 738.909us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 171.859us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 108.971us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 108.971us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 11.000s 2263.642us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 11.000s 2263.642us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 24.000s 2004.022us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 2963.382us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 55.000s 5979.023us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 192.573us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 598.132us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 19.668us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 45.411us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 158.388us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 158.388us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 42.318us 1 1 100.00
spi_host_csr_rw 1.000s 17.586us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.006us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.009us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 42.318us 1 1 100.00
spi_host_csr_rw 1.000s 17.586us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.006us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 135.096us 1 1 100.00
spi_host_tl_intg_err 2.000s 934.607us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 934.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 300.000s 13630.749us 1 1 100.00

Error Messages

   Test seed line log context