Simulation Results: sram_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 95.88 %
  • assert
  • 95.83 %
  • func
  • 94.06 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.04 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 28.440s 4761.397us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.780s 16.561us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.720s 52.505us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.160s 111.727us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 16.282us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.270s 715.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.720s 52.505us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 16.282us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 224.970s 27665.654us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 59.930s 6136.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 564.410s 85376.076us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 223.590s 83535.024us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 1433.190s 97582.342us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 34.790s 8518.080us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 39.530s 23761.064us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 296.480s 55211.022us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 15.930s 1919.902us 1 1 100.00
sram_ctrl_partial_access_b2b 333.650s 30430.356us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.570s 2696.778us 1 1 100.00
sram_ctrl_throughput_w_partial_write 26.100s 2987.672us 1 1 100.00
sram_ctrl_throughput_w_readback 46.650s 911.669us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 762.100s 49885.563us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.310s 679.492us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 3237.820s 157128.536us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.650s 38.060us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.820s 89.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.820s 89.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 16.561us 1 1 100.00
sram_ctrl_csr_rw 0.720s 52.505us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 16.282us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 42.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.780s 16.561us 1 1 100.00
sram_ctrl_csr_rw 0.720s 52.505us 1 1 100.00
sram_ctrl_csr_aliasing 0.710s 16.282us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.770s 42.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.680s 14696.550us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
sram_ctrl_tl_intg_err 2.150s 159.728us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.150s 159.728us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 762.100s 49885.563us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 762.100s 49885.563us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.720s 52.505us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 296.480s 55211.022us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 296.480s 55211.022us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 296.480s 55211.022us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 39.530s 23761.064us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.040s 674.960us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.680s 14696.550us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.800s 1352.677us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 28.440s 4761.397us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 28.440s 4761.397us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 296.480s 55211.022us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 39.530s 23761.064us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 28.440s 4761.397us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.830s 1.853us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.050s 566.639us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 89514553957936841726711694394340061992751488430572275945270544300397179520294 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1853407 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1853407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---