Simulation Results: sram_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.30 %
  • code
  • 96.07 %
  • assert
  • 95.79 %
  • func
  • 97.03 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.66 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.980s 309.438us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.830s 45.262us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.750s 13.713us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.020s 27.325us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 15.618us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.540s 127.998us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.750s 13.713us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 15.618us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.600s 2987.226us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.880s 584.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 557.000s 7178.049us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 156.720s 9712.540us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 48.580s 5059.876us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 515.260s 19265.874us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.850s 1224.754us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 1033.770s 37846.107us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.120s 589.052us 1 1 100.00
sram_ctrl_partial_access_b2b 219.450s 21960.972us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 32.730s 724.889us 1 1 100.00
sram_ctrl_throughput_w_partial_write 35.590s 546.957us 1 1 100.00
sram_ctrl_throughput_w_readback 14.080s 652.457us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 488.050s 12940.324us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.830s 32.559us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2220.630s 365910.112us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.750s 41.552us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.510s 52.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.510s 52.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.830s 45.262us 1 1 100.00
sram_ctrl_csr_rw 0.750s 13.713us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 15.618us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.030s 14.686us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.830s 45.262us 1 1 100.00
sram_ctrl_csr_rw 0.750s 13.713us 1 1 100.00
sram_ctrl_csr_aliasing 0.660s 15.618us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.030s 14.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.680s 245.540us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
sram_ctrl_tl_intg_err 1.450s 113.353us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.450s 113.353us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 488.050s 12940.324us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 488.050s 12940.324us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.750s 13.713us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 1033.770s 37846.107us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 1033.770s 37846.107us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 1033.770s 37846.107us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.850s 1224.754us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.260s 87.853us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.680s 245.540us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.150s 51.498us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.980s 309.438us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.980s 309.438us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 1033.770s 37846.107us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.850s 1224.754us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.980s 309.438us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 3.001us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 206.690s 5209.235us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 113882803209488743204703243104284640864910696726676677758421109509506199830331 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3001116 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3001116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---