uart Simulation Results

Simulation Results: uart

17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.74 %

code
96.77 %

assert
97.12 %

func
63.32 %

line
99.48 %

branch
98.14 %

cond
97.90 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.06%
V2S		100.00%
V3		100.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.430s	657.642us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.800s	53.068us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.630s	44.335us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.870s	59.286us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.720s	14.908us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.150s	230.545us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.630s	44.335us	1	1	100.00
	uart_csr_aliasing	0.720s	14.908us	1	1	100.00

33/34 passed

97.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	9.960s	62298.828us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.430s	657.642us	1	1	100.00
	uart_tx_rx	9.960s	62298.828us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	22.610s	19000.530us	1	1	100.00
	uart_rx_parity_err	19.310s	107380.253us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	9.960s	62298.828us	1	1	100.00
	uart_intr	22.610s	19000.530us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	32.980s	25849.369us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	31.150s	106459.770us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	14.230s	9949.145us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	22.610s	19000.530us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	22.610s	19000.530us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	22.610s	19000.530us	1	1	100.00
perf				1	1	100.00
	uart_perf	543.700s	16669.733us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	1.210s	655.262us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	1.210s	655.262us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	0.920s	64.963us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	5.910s	4065.970us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	5.060s	941.265us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	14.000s	4928.632us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	558.770s	86436.308us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	335.700s	370289.325us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.840s	13.903us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.790s	11.227us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.420s	47.290us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.420s	47.290us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.800s	53.068us	1	1	100.00
	uart_csr_rw	0.630s	44.335us	1	1	100.00
	uart_csr_aliasing	0.720s	14.908us	1	1	100.00
	uart_same_csr_outstanding	0.650s	13.518us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.800s	53.068us	1	1	100.00
	uart_csr_rw	0.630s	44.335us	1	1	100.00
	uart_csr_aliasing	0.720s	14.908us	1	1	100.00
	uart_same_csr_outstanding	0.650s	13.518us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.130s	74.748us	1	1	100.00
	uart_tl_intg_err	1.280s	75.637us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.280s	75.637us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	31.060s	7497.838us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_noise_filter	103476296816393472488340731419278116043167088324869627649536820101542252678316	71	UVM_ERROR @ 14507531 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 14780261 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 15052991 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 23234891 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 30689511 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0