| V1 |
|
100.00% |
| V2 |
|
94.44% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 11.050s | 2506.467us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 145.830s | 5485.360us | 1 | 1 | 100.00 | |
| xbar_random_delay | 6 | 6 | 100.00 | |||
| xbar_smoke_zero_delays | 4.070s | 91.590us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 186.790s | 31851.350us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 236.170s | 67971.281us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 35.560s | 227.046us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 108.060s | 51392.061us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 369.700s | 158460.157us | 1 | 1 | 100.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 9.630s | 386.965us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 14.720s | 445.935us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 13.330s | 266.625us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 14.720s | 445.935us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 1 | 2 | 50.00 | |||
| xbar_access_same_device | 27.220s | 178.889us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1095.390s | 600000.000us | 0 | 1 | 0.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 13.710s | 170.213us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 168.900s | 1457.281us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 827.870s | 41071.594us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 148.720s | 397.503us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 412.760s | 1284.802us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| xbar_access_same_device_slow_rsp | 50283697606822235679650390982108190110325079009855692914707466836606328541816 | 119 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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