Simulation Results: ac_range_check

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.67 %
  • code
  • 93.04 %
  • assert
  • 97.08 %
  • func
  • 57.88 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 80.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 33.000s 1217.327us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 49.000s 2162.255us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 37.901us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 205.059us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 1643.236us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1433.726us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 135.230us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 205.059us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1433.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 195.693us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 33.000s 1616.533us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 149.000s 10808.386us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 16.940us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 22.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 460.912us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 460.912us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 37.901us 1 1 100.00
ac_range_check_csr_rw 2.000s 205.059us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1433.726us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 48.983us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 37.901us 1 1 100.00
ac_range_check_csr_rw 2.000s 205.059us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 1433.726us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 48.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 9960.756us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 9960.756us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 9960.756us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 9960.756us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 66.000s 1368.093us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 11.640us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1238.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 260.000s 2727.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 439.742us 1 1 100.00

Error Messages

   Test seed line log context