| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
74.24% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 2.000s | 66.744us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 2.000s | 110.706us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 77.570us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 2.000s | 73.625us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 8.000s | 11564.220us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 3.000s | 201.974us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 93.235us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 2.000s | 73.625us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 201.974us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 110.706us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 68.415us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 2.000s | 110.706us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 68.415us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| aes_b2b | 3.000s | 152.721us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 110.706us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 68.415us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 59.080us | 1 | 1 | 100.00 | |
| aes_config_error | 3.000s | 68.415us | 1 | 1 | 100.00 | |
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 3.000s | 158.296us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 4.000s | 190.764us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 114.204us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 3.000s | 99.192us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 19.000s | 2100.315us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 1.000s | 102.409us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 3.000s | 231.915us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 3.000s | 231.915us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 77.570us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 73.625us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 201.974us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 496.430us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 77.570us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 73.625us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 3.000s | 201.974us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 496.430us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 3.000s | 87.825us | 1 | 1 | 100.00 | |
| fault_inject | 1 | 3 | 33.33 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 4.000s | 573.355us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 16.000s | 10313.882us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 2.000s | 179.565us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 2.000s | 179.565us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 2.000s | 110.706us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| aes_core_fi | 2.000s | 139.363us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 2 | 2 | 100.00 | |||
| aes_config_error | 3.000s | 68.415us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 381.879us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 114.204us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 2.000s | 92.828us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 3.000s | 92.152us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_redun | 2 | 4 | 50.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_redun | 1 | 3 | 33.33 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cipher_ctr_redun | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_sparse | 1 | 1 | 100.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_sparse | 2 | 4 | 50.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 74.008us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 2 | 4 | 50.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 2 | 4 | 50.00 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 2.000s | 59.425us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_local_esc | 1 | 3 | 33.33 | |||
| aes_fi | 2.000s | 216.088us | 1 | 1 | 100.00 | |
| aes_control_fi | 33.000s | 10003.779us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 2.000s | 39.799us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! | ||||
| aes_control_fi | 48490648097473433719857734483769802264536813082137254654566211119487245245494 | 141 |
UVM_FATAL @ 10003779307 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003779307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| aes_cipher_fi | 53766001916281400238767209137108952100028713243647539291550793600655152674606 | None |
Job timed out after 1 minutes
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 26862071293849860620282828678580079062508012676305235138905298035950166780959 | 146 |
UVM_FATAL @ 39799434 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 39799434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|