clkmgr Simulation Results

Simulation Results: clkmgr

18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
75.81 %

code
68.98 %

assert
89.88 %

func
68.56 %

line
81.79 %

branch
86.59 %

cond
79.46 %

toggle
97.08 %

FSM
0.00 %

Validation stages

V1		50.00%
V2		57.89%
V2S		35.29%
V3		0.00%

4/8 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	clkmgr_smoke	0.960s	33.041us	1	1	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.150s	35.129us	1	1	100.00
csr_rw				0	1	0.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.290s	23.726us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.060s	19.620us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	clkmgr_csr_mem_rw_with_rand_reset	1.140s	24.212us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				1	2	50.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
	clkmgr_csr_aliasing	1.060s	19.620us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				1	1	100.00
	clkmgr_peri	0.770s	19.208us	1	1	100.00
trans_enables				1	1	100.00
	clkmgr_trans	0.950s	18.012us	1	1	100.00
clk_status				1	1	100.00
	clkmgr_clk_status	0.750s	20.078us	1	1	100.00
jitter				1	1	100.00
	clkmgr_smoke	0.960s	33.041us	1	1	100.00
frequency				0	1	0.00
	clkmgr_frequency	0.750s	17.613us	0	1	0.00
frequency_timeout				0	1	0.00
	clkmgr_frequency_timeout	0.610s	5.255us	0	1	0.00
frequency_overflow				0	1	0.00
	clkmgr_frequency	0.750s	17.613us	0	1	0.00
stress_all				0	1	0.00
	clkmgr_stress_all	0.870s	8.883us	0	1	0.00
alert_test				1	1	100.00
	clkmgr_alert_test	1.070s	42.979us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	clkmgr_tl_errors	3.880s	254.808us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	clkmgr_tl_errors	3.880s	254.808us	1	1	100.00
tl_d_outstanding_access				2	4	50.00
	clkmgr_csr_hw_reset	1.150s	35.129us	1	1	100.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
	clkmgr_csr_aliasing	1.060s	19.620us	1	1	100.00
	clkmgr_same_csr_outstanding	0.730s	3.992us	0	1	0.00
tl_d_partial_access				2	4	50.00
	clkmgr_csr_hw_reset	1.150s	35.129us	1	1	100.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
	clkmgr_csr_aliasing	1.060s	19.620us	1	1	100.00
	clkmgr_same_csr_outstanding	0.730s	3.992us	0	1	0.00

V2S

6/17 passed

35.29 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	clkmgr_tl_intg_err	0.980s	34.872us	0	1	0.00
	clkmgr_sec_cm	0.810s	9.923us	0	1	0.00
shadow_reg_update_error				1	1	100.00
	clkmgr_shadow_reg_errors	1.240s	43.650us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	clkmgr_shadow_reg_errors	1.240s	43.650us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	clkmgr_shadow_reg_errors	1.240s	43.650us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	clkmgr_shadow_reg_errors	1.240s	43.650us	1	1	100.00
shadow_reg_update_error_with_csr_rw				0	1	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	0.960s	16.232us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	clkmgr_tl_intg_err	0.980s	34.872us	0	1	0.00
sec_cm_meas_clk_bkgn_chk				0	1	0.00
	clkmgr_frequency	0.750s	17.613us	0	1	0.00
sec_cm_timeout_clk_bkgn_chk				0	1	0.00
	clkmgr_frequency_timeout	0.610s	5.255us	0	1	0.00
sec_cm_meas_config_shadow				1	1	100.00
	clkmgr_shadow_reg_errors	1.240s	43.650us	1	1	100.00
sec_cm_idle_intersig_mubi				1	1	100.00
	clkmgr_idle_intersig_mubi	1.120s	38.890us	1	1	100.00
sec_cm_jitter_config_mubi				0	1	0.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
sec_cm_idle_ctr_redun				0	1	0.00
	clkmgr_sec_cm	0.810s	9.923us	0	1	0.00
sec_cm_meas_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
sec_cm_clk_ctrl_config_regwen				0	1	0.00
	clkmgr_csr_rw	0.860s	14.578us	0	1	0.00
prim_count_check				0	1	0.00
	clkmgr_sec_cm	0.810s	9.923us	0	1	0.00

0/2 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				1
	clkmgr_regwen	0.720s	11.964us	1
stress_all_with_rand_reset				1
	clkmgr_stress_all_with_rand_reset	0.970s	20.037us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:
	clkmgr_shadow_reg_errors_with_csr_rw	47290300887645550775010481592812425584266809612914420929532694057615994967441	72	UVM_ERROR @ 16231989 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 16231989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	79992092014710224182045902369561350687581396782779013784105944944728890476899	94	UVM_ERROR @ 34871534 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 34871534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	44490617596562734505841642724340956046908597687753131349092233704680335563315	72	UVM_ERROR @ 14578398 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 14578398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	56193316330728561866691506217581590754754710163464838840824093983283784393795	73	UVM_ERROR @ 24211843 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 UVM_INFO @ 24211843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:
	clkmgr_csr_bit_bash	40762836142027217432592322582368920263602558909235655820959987714111695345953	72	UVM_ERROR @ 23725526 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0 UVM_INFO @ 23725526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch
	clkmgr_same_csr_outstanding	34289214101178560549434612905115525818315862732028483734551127602030177990475	72	UVM_ERROR @ 3992243 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0xb058dca4 read out mismatch UVM_INFO @ 3992243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b
	clkmgr_frequency	114674623487220083281133815053373419226541265090429955688224959726555776278269	73	UVM_ERROR @ 17612818 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00 UVM_INFO @ 17612818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	45003571643714479446512001186115169334077684525099157019043617385422168457963	74	UVM_ERROR @ 8883390 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00 UVM_INFO @ 8883390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b
	clkmgr_frequency_timeout	5009008840750944007420988876714649031423188390621935915192589538670154592709	75	UVM_ERROR @ 5255204 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00 UVM_INFO @ 5255204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	40020359182602344141995610188252288530807035048275248845164085773659789690728	90	UVM_ERROR @ 20036500 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00 UVM_INFO @ 20036500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
	clkmgr_regwen	17525862995479149074306093335652592688808586639022280587376942251223792389055	71	UVM_ERROR @ 11964184 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 6 [0x6]) reg name: clkmgr_reg_block.io_meas_ctrl_en UVM_INFO @ 11964184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	25380729468595535237984829273970293287570471154237849160323443149913729409601	79	UVM_ERROR @ 9922629 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 9922629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---