Simulation Results: edn

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.91 %
  • code
  • 80.52 %
  • assert
  • 95.66 %
  • func
  • 81.55 %
  • line
  • 97.61 %
  • branch
  • 91.77 %
  • cond
  • 86.83 %
  • toggle
  • 75.83 %
  • FSM
  • 50.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 18.506us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 35.329us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 25.079us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.220s 60.857us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.190s 66.146us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 77.361us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 25.079us 1 1 100.00
edn_csr_aliasing 1.190s 66.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 65.767us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 65.767us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 65.767us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.790s 29.744us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 35.393us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 45.828us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 11.281us 1 1 100.00
edn_disable_auto_req_mode 0.860s 45.576us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.240s 1009.172us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 22.762us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 67.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.270s 79.818us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.270s 79.818us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 35.329us 1 1 100.00
edn_csr_rw 0.760s 25.079us 1 1 100.00
edn_csr_aliasing 1.190s 66.146us 1 1 100.00
edn_same_csr_outstanding 1.190s 37.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 35.329us 1 1 100.00
edn_csr_rw 0.760s 25.079us 1 1 100.00
edn_csr_aliasing 1.190s 66.146us 1 1 100.00
edn_same_csr_outstanding 1.190s 37.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
edn_tl_intg_err 1.180s 154.893us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.900s 52.670us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 35.393us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 35.393us 1 1 100.00
edn_sec_cm 3.780s 282.592us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 35.393us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.180s 154.893us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 72.480s 3981.980us 1 1 100.00

Error Messages

   Test seed line log context