Simulation Results: edn

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.14 %
  • code
  • 83.39 %
  • assert
  • 97.14 %
  • func
  • 80.88 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 90.31 %
  • toggle
  • 88.06 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 18.134us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.710s 45.607us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.650s 18.017us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.870s 488.256us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.100s 176.132us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.870s 18.183us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.650s 18.017us 1 1 100.00
edn_csr_aliasing 1.100s 176.132us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.980s 72.936us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.980s 72.936us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.980s 72.936us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 20.702us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.840s 55.130us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 29.934us 1 1 100.00
disable 2 2 100.00
edn_disable 0.690s 21.214us 1 1 100.00
edn_disable_auto_req_mode 0.810s 23.049us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.040s 127.003us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.710s 14.069us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.740s 27.697us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.650s 229.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.650s 229.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.710s 45.607us 1 1 100.00
edn_csr_rw 0.650s 18.017us 1 1 100.00
edn_csr_aliasing 1.100s 176.132us 1 1 100.00
edn_same_csr_outstanding 0.750s 42.338us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.710s 45.607us 1 1 100.00
edn_csr_rw 0.650s 18.017us 1 1 100.00
edn_csr_aliasing 1.100s 176.132us 1 1 100.00
edn_same_csr_outstanding 0.750s 42.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
edn_tl_intg_err 1.160s 104.836us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 19.909us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.840s 55.130us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.840s 55.130us 1 1 100.00
edn_sec_cm 3.780s 1207.229us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.840s 55.130us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.160s 104.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.750s 10057.412us 1 1 100.00

Error Messages

   Test seed line log context