Simulation Results: hmac

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.31 %
  • code
  • 97.33 %
  • assert
  • 97.61 %
  • func
  • 43.00 %
  • line
  • 99.84 %
  • branch
  • 99.50 %
  • cond
  • 96.12 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.570s 281.742us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 21.193us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.710s 46.939us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.380s 2912.746us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.780s 675.110us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.290s 19.130us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.710s 46.939us 1 1 100.00
hmac_csr_aliasing 4.780s 675.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 28.000s 590.736us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 64.130s 2967.915us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 165.320s 19552.727us 1 1 100.00
hmac_test_sha384_vectors 21.290s 1031.265us 1 1 100.00
hmac_test_sha512_vectors 20.230s 999.492us 1 1 100.00
hmac_test_hmac256_vectors 6.500s 366.825us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 386.383us 1 1 100.00
hmac_test_hmac512_vectors 11.570s 336.133us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.270s 1384.236us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 355.570s 2364.026us 1 1 100.00
error 1 1 100.00
hmac_error 41.090s 1999.313us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 71.540s 2137.807us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.570s 281.742us 1 1 100.00
hmac_long_msg 28.000s 590.736us 1 1 100.00
hmac_back_pressure 64.130s 2967.915us 1 1 100.00
hmac_datapath_stress 355.570s 2364.026us 1 1 100.00
hmac_burst_wr 13.270s 1384.236us 1 1 100.00
hmac_stress_all 14.430s 7951.717us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.570s 281.742us 1 1 100.00
hmac_long_msg 28.000s 590.736us 1 1 100.00
hmac_back_pressure 64.130s 2967.915us 1 1 100.00
hmac_datapath_stress 355.570s 2364.026us 1 1 100.00
hmac_wipe_secret 71.540s 2137.807us 1 1 100.00
hmac_test_sha256_vectors 165.320s 19552.727us 1 1 100.00
hmac_test_sha384_vectors 21.290s 1031.265us 1 1 100.00
hmac_test_sha512_vectors 20.230s 999.492us 1 1 100.00
hmac_test_hmac256_vectors 6.500s 366.825us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 386.383us 1 1 100.00
hmac_test_hmac512_vectors 11.570s 336.133us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.570s 281.742us 1 1 100.00
hmac_long_msg 28.000s 590.736us 1 1 100.00
hmac_back_pressure 64.130s 2967.915us 1 1 100.00
hmac_datapath_stress 355.570s 2364.026us 1 1 100.00
hmac_burst_wr 13.270s 1384.236us 1 1 100.00
hmac_error 41.090s 1999.313us 1 1 100.00
hmac_wipe_secret 71.540s 2137.807us 1 1 100.00
hmac_test_sha256_vectors 165.320s 19552.727us 1 1 100.00
hmac_test_sha384_vectors 21.290s 1031.265us 1 1 100.00
hmac_test_sha512_vectors 20.230s 999.492us 1 1 100.00
hmac_test_hmac256_vectors 6.500s 366.825us 1 1 100.00
hmac_test_hmac384_vectors 11.640s 386.383us 1 1 100.00
hmac_test_hmac512_vectors 11.570s 336.133us 1 1 100.00
hmac_stress_all 14.430s 7951.717us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 14.430s 7951.717us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.850s 34.269us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.740s 46.720us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.850s 76.643us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.850s 76.643us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 21.193us 1 1 100.00
hmac_csr_rw 0.710s 46.939us 1 1 100.00
hmac_csr_aliasing 4.780s 675.110us 1 1 100.00
hmac_same_csr_outstanding 1.420s 237.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 21.193us 1 1 100.00
hmac_csr_rw 0.710s 46.939us 1 1 100.00
hmac_csr_aliasing 4.780s 675.110us 1 1 100.00
hmac_same_csr_outstanding 1.420s 237.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 2.400s 2221.119us 1 1 100.00
hmac_sec_cm 1.340s 239.451us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.400s 2221.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.570s 281.742us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.920s 171.906us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 97.350s 3627.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.180s 23.941us 1 1 100.00

Error Messages

   Test seed line log context