i2c Simulation Results

Simulation Results: i2c

18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.39 %

code
81.43 %

assert
96.19 %

func
78.54 %

line
96.41 %

branch
92.26 %

cond
84.78 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		89.80%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	11.830s	4821.053us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.020s	604.328us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.780s	52.839us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.640s	22.602us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.770s	141.937us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.390s	208.014us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.090s	30.810us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.640s	22.602us	1	1	100.00
	i2c_csr_aliasing	1.390s	208.014us	1	1	100.00

44/49 passed

89.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.620s	5.704us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	945.670s	17650.650us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	10.650s	2965.832us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.640s	106.710us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	46.090s	14089.955us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	43.900s	4676.463us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.880s	155.627us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.220s	1987.178us	1	1	100.00
	i2c_host_fifo_reset_rx	4.170s	257.680us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	92.870s	5572.812us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.880s	1046.485us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.450s	116.118us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.870s	1099.307us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	53.150s	44095.500us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.840s	1994.509us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	13.840s	1099.999us	1	1	100.00
	i2c_target_intr_smoke	3.340s	1852.941us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.990s	203.372us	1	1	100.00
	i2c_target_fifo_reset_tx	0.950s	271.051us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	169.050s	34048.816us	1	1	100.00
	i2c_target_stress_rd	13.840s	1099.999us	1	1	100.00
	i2c_target_intr_stress_wr	3.180s	14070.364us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.810s	2160.978us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	3.580s	10009.029us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.440s	2334.283us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	15.620s	10014.028us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.740s	4900.013us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.220s	133.950us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	10.650s	2965.832us	1	1	100.00
	i2c_host_perf_precise	6.680s	2731.723us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.880s	1046.485us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.560s	171.509us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.760s	2488.892us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.560s	752.463us	1	1	100.00
	i2c_target_nack_txstretch	1.200s	1338.994us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.170s	772.534us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.750s	1028.814us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.650s	68.706us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.670s	23.054us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.040s	50.073us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.040s	50.073us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	52.839us	1	1	100.00
	i2c_csr_rw	0.640s	22.602us	1	1	100.00
	i2c_csr_aliasing	1.390s	208.014us	1	1	100.00
	i2c_same_csr_outstanding	0.710s	35.318us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	52.839us	1	1	100.00
	i2c_csr_rw	0.640s	22.602us	1	1	100.00
	i2c_csr_aliasing	1.390s	208.014us	1	1	100.00
	i2c_same_csr_outstanding	0.710s	35.318us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_sec_cm	0.810s	43.433us	1	1	100.00
	i2c_tl_intg_err	1.680s	1528.941us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.680s	1528.941us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.440s	1088.217us	1
target_error_intr				1
	i2c_target_unexp_stop	0.970s	121.099us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	18.510s	6102.363us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	7786060405153259826310676525130297887181508403961628371716844429287201664998	83	UVM_ERROR @ 5703509 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 5703509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	38003356042509560278120499277604247532683984648604085426562325593862984471365	81	UVM_ERROR @ 1099307429 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 1099307429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
	i2c_target_stretch	70617142843613527449456195315998574939078004002326775959181826496618874184637	75	UVM_FATAL @ 10009029036 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! UVM_INFO @ 10009029036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	87739542023388265719316775537670288637134096743064884020440062976007137214595	75	UVM_ERROR @ 121099408 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1]) UVM_INFO @ 121099408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	106165417269307000447887412457329840855496879427855338857952056820025491854903	76	UVM_FATAL @ 10014027956 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10014027956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	15467866885223745684216611580251876232605697368263499015201927223405172060032	82	UVM_ERROR @ 1088217317 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1088217317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	12366965222980884737549032463781129058262748144951904936408619204899702361382	112	UVM_ERROR @ 6102362591 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 6102362591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_mode_toggle	76128274432019367546139577945512834267815565172248217357021079632585805367536	82	UVM_ERROR @ 116118016 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared: ---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @31316