| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
100.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 26.960s | 825.603us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 0.850s | 281.403us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 0.860s | 17.312us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 9.870s | 292.247us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 6.270s | 438.584us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 1.720s | 34.148us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 0.860s | 17.312us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 6.270s | 438.584us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.940s | 41.681us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 1.060s | 26.592us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 1061.270s | 84383.324us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 221.220s | 3584.921us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 1592.770s | 244988.679us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 1132.140s | 17531.148us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 808.190s | 25940.130us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 576.560s | 11932.701us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 152.570s | 34161.841us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 211.690s | 10778.447us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 1.710s | 65.216us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 1.410s | 28.581us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 86.760s | 6322.220us | 1 | 1 | 100.00 | |
| app | 1 | 1 | 100.00 | |||
| kmac_app | 162.110s | 51279.943us | 1 | 1 | 100.00 | |
| app_with_partial_data | 1 | 1 | 100.00 | |||
| kmac_app_with_partial_data | 117.430s | 8724.444us | 1 | 1 | 100.00 | |
| entropy_refresh | 1 | 1 | 100.00 | |||
| kmac_entropy_refresh | 63.910s | 3653.325us | 1 | 1 | 100.00 | |
| error | 1 | 1 | 100.00 | |||
| kmac_error | 254.210s | 4616.358us | 1 | 1 | 100.00 | |
| key_error | 1 | 1 | 100.00 | |||
| kmac_key_error | 3.890s | 1826.416us | 1 | 1 | 100.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 114.840s | 10043.385us | 0 | 1 | 0.00 | |
| edn_timeout_error | 1 | 1 | 100.00 | |||
| kmac_edn_timeout_error | 5.710s | 1468.861us | 1 | 1 | 100.00 | |
| entropy_mode_error | 1 | 1 | 100.00 | |||
| kmac_entropy_mode_error | 23.480s | 6339.793us | 1 | 1 | 100.00 | |
| entropy_ready_error | 1 | 1 | 100.00 | |||
| kmac_entropy_ready_error | 38.780s | 12661.175us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.340s | 38.451us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| kmac_stress_all | 594.950s | 88648.883us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 0.670s | 44.655us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.990s | 73.653us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 2.230s | 491.904us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 2.230s | 491.904us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.850s | 281.403us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.860s | 17.312us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 6.270s | 438.584us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.290s | 188.486us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.850s | 281.403us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.860s | 17.312us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 6.270s | 438.584us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.290s | 188.486us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.780s | 102.063us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.780s | 102.063us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.780s | 102.063us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.780s | 102.063us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 1.920s | 172.926us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| kmac_tl_intg_err | 1.780s | 102.767us | 1 | 1 | 100.00 | |
| kmac_sec_cm | 64.870s | 54262.791us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 1.780s | 102.767us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.340s | 38.451us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 26.960s | 825.603us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 86.760s | 6322.220us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.780s | 102.063us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 64.870s | 54262.791us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 64.870s | 54262.791us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 64.870s | 54262.791us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 26.960s | 825.603us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.340s | 38.451us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 64.870s | 54262.791us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 1 | 1 | 100.00 | |||
| kmac_mubi | 169.900s | 9214.005us | 1 | 1 | 100.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 26.960s | 825.603us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 59.310s | 2617.824us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | ||||
| kmac_sideload_invalid | 91809210739914980664615267525634340385210022653595398950311879325905906722912 | 84 |
UVM_FATAL @ 10043384644 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x36f19000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10043384644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) | ||||
| kmac_stress_all_with_rand_reset | 37657868374757929595361972449928320475075603916175999155049888805331075028078 | 209 |
UVM_ERROR @ 2617824152 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2617824152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|