Simulation Results: lc_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.01 %
  • code
  • 89.58 %
  • assert
  • 95.99 %
  • func
  • 90.47 %
  • line
  • 97.69 %
  • branch
  • 96.56 %
  • cond
  • 79.67 %
  • toggle
  • 83.49 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
90.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.710s 81.825us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 18.302us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.348us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.160s 106.673us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 60.529us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.980s 215.872us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 27.348us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 60.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.610s 66.294us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.660s 2069.776us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.720s 23.024us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.060s 108.013us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.980s 2245.572us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_prog_failure 2.060s 108.013us 1 1 100.00
lc_ctrl_errors 10.980s 2245.572us 1 1 100.00
lc_ctrl_security_escalation 6.090s 1590.643us 1 1 100.00
lc_ctrl_jtag_state_failure 6.960s 192.568us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.590s 1207.250us 1 1 100.00
lc_ctrl_jtag_errors 29.600s 15909.367us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 2.490s 526.640us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.540s 214.952us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 21.610s 4991.691us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.590s 6823.142us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.040s 19.906us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.880s 3840.621us 1 1 100.00
lc_ctrl_jtag_alert_test 1.610s 218.154us 1 1 100.00
lc_ctrl_jtag_smoke 6.140s 1165.688us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.920s 1344.447us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.590s 1207.250us 1 1 100.00
lc_ctrl_jtag_errors 29.600s 15909.367us 1 1 100.00
lc_ctrl_jtag_access 5.180s 636.017us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.460s 4489.725us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.320s 3089.504us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 14.568us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 17.110s 1568.907us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 28.683us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.440s 44.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.440s 44.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.302us 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.348us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 60.529us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 24.597us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 18.302us 1 1 100.00
lc_ctrl_csr_rw 0.950s 27.348us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 60.529us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 24.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.390s 130.198us 1 1 100.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.390s 130.198us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.660s 2069.776us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.520s 161.377us 0 1 0.00
lc_ctrl_sec_cm 6.220s 2257.903us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.090s 1590.643us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 4.610s 66.294us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.920s 1344.447us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.220s 1331.889us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.220s 1331.889us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.970s 1429.058us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.960s 266.834us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.960s 266.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.620s 277.712us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 85531868367833879178278566246830883503238731847859005152793991160910190473800 1058
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 161376682 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 161376682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 7041008418670210271071949544049669929314623471486122921536980488759286003797 372
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 192567845 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 192567845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 54334841801936685221471419584931093163125496387032301459673022441523965200638 693
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1344447329 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1344447329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80886707064192534469254420350465840634048109378183333132825429972158122220317 625
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 277712093 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 277712093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---