Simulation Results: lc_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 87.30 %
  • assert
  • 95.99 %
  • func
  • 88.13 %
  • line
  • 97.45 %
  • branch
  • 95.38 %
  • cond
  • 79.15 %
  • toggle
  • 83.11 %
  • FSM
  • 81.40 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.190s 113.248us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.750s 42.786us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.820s 27.003us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.690s 51.719us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 36.652us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.090s 74.239us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.820s 27.003us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 36.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.080s 207.190us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.100s 2675.565us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.120s 95.332us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.360s 105.479us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.590s 3823.212us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_prog_failure 1.360s 105.479us 1 1 100.00
lc_ctrl_errors 10.590s 3823.212us 1 1 100.00
lc_ctrl_security_escalation 6.260s 2803.326us 1 1 100.00
lc_ctrl_jtag_state_failure 2.590s 106.581us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.370s 1306.084us 1 1 100.00
lc_ctrl_jtag_errors 15.010s 1574.771us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.240s 169.379us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.550s 308.886us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.010s 469.007us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.390s 326.040us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.960s 94.824us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.220s 215.751us 1 1 100.00
lc_ctrl_jtag_alert_test 1.010s 57.269us 1 1 100.00
lc_ctrl_jtag_smoke 6.260s 1473.835us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.970s 1993.321us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.370s 1306.084us 1 1 100.00
lc_ctrl_jtag_errors 15.010s 1574.771us 1 1 100.00
lc_ctrl_jtag_access 12.500s 750.473us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.160s 27892.223us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.040s 4147.342us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.090s 18.027us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 6.840s 1430.468us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.280s 65.541us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 55.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 55.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 42.786us 1 1 100.00
lc_ctrl_csr_rw 0.820s 27.003us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 36.652us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 183.167us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.750s 42.786us 1 1 100.00
lc_ctrl_csr_rw 0.820s 27.003us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 36.652us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 183.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.840s 116.268us 1 1 100.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 116.268us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.100s 2675.565us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 1.150s 4.378us 0 1 0.00
lc_ctrl_sec_cm 7.760s 671.103us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.260s 2803.326us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.080s 207.190us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.970s 1993.321us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.640s 1987.181us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.640s 1987.181us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.420s 2918.052us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.620s 1266.785us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.620s 1266.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 8.890s 1348.486us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 53104659565586221963971720518731828478498847492161564703895566046161898395677 121
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 4378443 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4378443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 89186965385061891828236675164247216115367050469659940153714409085335811529998 192
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 106581423 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 106581423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 58910572454637458534419262067714817843545938447898161531340499863280648884863 550
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1993320537 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1993320537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 99617829361572397408421331039875804623826965127979770151775097568727422807183 243
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1430468420 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1430468420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60408584665233446622054280572365250375004504245318749688754734181561050823921 804
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 1348486118 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 1348486118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---