Simulation Results: mbx

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.99 %
  • code
  • 88.98 %
  • assert
  • 96.81 %
  • func
  • 84.18 %
  • block
  • 94.58 %
  • line
  • 94.67 %
  • branch
  • 86.31 %
  • toggle
  • 85.96 %
Validation stages
V1
100.00%
V2
81.25%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 61.000s 10575.608us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 45.330us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 18.487us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 218.955us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 185.294us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 2.000s 25.304us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 18.487us 1 1 100.00
mbx_csr_aliasing 2.000s 185.294us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 1.000s 5.185us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 69.620us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 11.000s 4348.774us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 18.000s 1200.405us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 24.231us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 15.708us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
mbx_tl_errors 4.000s 42.462us 1 1 100.00
tl_d_illegal_access 1 1 100.00
mbx_tl_errors 4.000s 42.462us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 45.330us 1 1 100.00
mbx_csr_rw 1.000s 18.487us 1 1 100.00
mbx_csr_aliasing 2.000s 185.294us 1 1 100.00
mbx_same_csr_outstanding 2.000s 126.388us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 45.330us 1 1 100.00
mbx_csr_rw 1.000s 18.487us 1 1 100.00
mbx_csr_aliasing 2.000s 185.294us 1 1 100.00
mbx_same_csr_outstanding 2.000s 126.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_sec_cm 2.000s 14.419us 1 1 100.00
mbx_tl_intg_err 1.000s 270.275us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register
mbx_stress 6732537546145234344425655721157918331400677599129504504643443454008977545648 86
UVM_ERROR @ 5185370 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 5185370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_imbx_oob 93584765964334096132580952981922756937075747711310254254034682210785980393690 146
UVM_ERROR @ 4348774093 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 4348774093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched
mbx_stress_zero_delays 4869020545088158657074791484489324791352057699930141877041018826954653428927 209
UVM_ERROR @ 69620327 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 1300831091 [0x4d891b73]) RDATA read data mismatched
UVM_INFO @ 69620327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---