Simulation Results: otbn

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.10 %
  • code
  • 95.51 %
  • assert
  • 88.93 %
  • func
  • 97.86 %
  • block
  • 99.45 %
  • line
  • 99.58 %
  • branch
  • 93.61 %
  • toggle
  • 91.41 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.39%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 44.842us 1 1 100.00
single_binary 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 16.148us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 20.970us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 94.938us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 128.389us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 220.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 20.970us 1 1 100.00
otbn_csr_aliasing 3.000s 128.389us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 21.000s 1725.209us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 17.000s 4297.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 17.000s 209.372us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 40.000s 341.239us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 68.000s 915.595us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 65.000s 228.218us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 26.734us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 41.234us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 24.313us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 28.782us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 173.093us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 119.563us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 119.563us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 16.148us 1 1 100.00
otbn_csr_rw 3.000s 20.970us 1 1 100.00
otbn_csr_aliasing 3.000s 128.389us 1 1 100.00
otbn_same_csr_outstanding 4.000s 122.516us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 16.148us 1 1 100.00
otbn_csr_rw 3.000s 20.970us 1 1 100.00
otbn_csr_aliasing 3.000s 128.389us 1 1 100.00
otbn_same_csr_outstanding 4.000s 122.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 5.000s 50.877us 1 1 100.00
otbn_dmem_err 6.000s 13.947us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 114.098us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 67.577us 1 1 100.00
otbn_mac_bignum_acc_err 34.000s 181.543us 1 1 100.00
otbn_urnd_err 5.000s 10.080us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 9.891us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 53.000us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 9.000s 49.556us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
otbn_tl_intg_err 19.000s 123.876us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 8.000s 90.029us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 44.842us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 13.947us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 5.000s 50.877us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 19.000s 123.876us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 26.734us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 50.877us 1 1 100.00
otbn_dmem_err 6.000s 13.947us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 41.234us 1 1 100.00
otbn_illegal_mem_acc 4.000s 9.891us 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 50.877us 1 1 100.00
otbn_dmem_err 6.000s 13.947us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 41.234us 1 1 100.00
otbn_illegal_mem_acc 4.000s 9.891us 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 26.734us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 5.000s 50.877us 1 1 100.00
otbn_dmem_err 6.000s 13.947us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 41.234us 1 1 100.00
otbn_illegal_mem_acc 4.000s 9.891us 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 74.535us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 39.898us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 36.000s 141.394us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 36.000s 141.394us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 37.480us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 56.719us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 23.191us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 23.191us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 30.813us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 68.000s 915.595us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 75.724us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 12.000s 114.140us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 154.000s 3691.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 122.000s 566.636us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 65466143366334696459317872685562456576885025278853194670411166552459741420248 271
UVM_ERROR @ 566636193 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 566636193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 56810467467137519554779717175625114688465779141645781118471297289206101780903 113
UVM_FATAL @ 90028898 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 90028898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---