Simulation Results: otp_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.33 %
  • code
  • 70.68 %
  • assert
  • 93.06 %
  • func
  • 53.25 %
  • line
  • 87.35 %
  • branch
  • 83.86 %
  • cond
  • 85.80 %
  • toggle
  • 61.04 %
  • FSM
  • 35.35 %
Validation stages
V1
90.91%
V2
68.00%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.910s 223.615us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.830s 1709.828us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.800s 819.291us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.950s 893.776us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.280s 178.671us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.160s 141.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.800s 819.291us 1 1 100.00
otp_ctrl_csr_aliasing 4.280s 178.671us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.470s 78.987us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.420s 47.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 115.650s 6448.994us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.560s 169.665us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 6.320s 750.287us 0 1 0.00
otp_ctrl_check_fail 7.710s 1131.222us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 8.260s 235.787us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 12.000s 631.503us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 18.400s 2944.989us 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 45.810s 1599.707us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 11.340s 4541.090us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 6.010s 680.927us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 167.100s 53004.860us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.210s 643.656us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.190s 973.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.930s 261.583us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.930s 261.583us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.830s 1709.828us 1 1 100.00
otp_ctrl_csr_rw 2.800s 819.291us 1 1 100.00
otp_ctrl_csr_aliasing 4.280s 178.671us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.140s 580.606us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.830s 1709.828us 1 1 100.00
otp_ctrl_csr_rw 2.800s 819.291us 1 1 100.00
otp_ctrl_csr_aliasing 4.280s 178.671us 1 1 100.00
otp_ctrl_same_csr_outstanding 4.140s 580.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 15.290s 12150.772us 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.290s 12150.772us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_macro_errs 11.340s 4541.090us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_macro_errs 11.340s 4541.090us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.780s 8098.997us 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.560s 169.665us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.710s 1131.222us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 5.890s 933.049us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 266.990s 35887.782us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 8.260s 235.787us 0 1 0.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.990s 426.792us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 11.340s 4541.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 63.080s 22344.128us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 2.360s 34.267us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_smoke 103644816431242439921452207368871026106294980499409823954349111788484932181360 4791
UVM_ERROR @ 426792310 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 426792310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 45598694631505019244924216335654397682785259661308571963154020008110552655518 9801
UVM_ERROR @ 235787210 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 235787210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 38458653085482541971662570520174306569333663377208587360735273409744008141879 112494
UVM_ERROR @ 6448994362 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 6448994362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 50906237072278848398387722357549024525440925025033719911353677782144492079953 86
UVM_ERROR @ 22344127750 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 22344127750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 3434491412730986180974398834238264259384587209445462183182600478123165807108 29734
UVM_ERROR @ 53004859578 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 53004859578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_background_chks 109237878906961904481589415476113933243100326391703233387626256363930944423256 7132
UVM_ERROR @ 750286599 ps: (otp_ctrl_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 750286599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 16639740297321457586451956440024768906919517850966982499696218335754855624917 3364
UVM_ERROR @ 933049358 ps: (otp_ctrl_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 933049358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 90376812960951082334089026834672205623699470299794132043525455460707198304247 6239
UVM_ERROR @ 1131221613 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1131221613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_parallel_key_req 45276454609085335378648828552222144630614863850393501749652807741434784923622 10362
UVM_ERROR @ 631503475 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 631503475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 84060391792363543036558784925577547426576439160545235663047323527554967852018 2357
UVM_ERROR @ 680926850 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 680926850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 71638213304686140339226148635707350277746445532446605665928558104528153852429 97
UVM_ERROR @ 34267319 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 34267319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---