Simulation Results: rom_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.28 %
  • code
  • 97.89 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 97.92 %
  • toggle
  • 99.95 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.810s 3991.625us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.720s 620.796us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.820s 698.810us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.580s 1066.684us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.320s 1065.201us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.190s 314.896us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.820s 698.810us 1 1 100.00
rom_ctrl_csr_aliasing 9.320s 1065.201us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.610s 215.945us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.990s 260.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.740s 333.032us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 18.690s 578.799us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.580s 564.075us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.450s 4982.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.410s 210.073us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.410s 210.073us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.720s 620.796us 1 1 100.00
rom_ctrl_csr_rw 5.820s 698.810us 1 1 100.00
rom_ctrl_csr_aliasing 9.320s 1065.201us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.980s 1066.279us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.720s 620.796us 1 1 100.00
rom_ctrl_csr_rw 5.820s 698.810us 1 1 100.00
rom_ctrl_csr_aliasing 9.320s 1065.201us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.980s 1066.279us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.870s 6104.354us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
rom_ctrl_tl_intg_err 51.760s 308.264us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.810s 3991.625us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.810s 3991.625us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.810s 3991.625us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.760s 308.264us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
rom_ctrl_kmac_err_chk 14.580s 564.075us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 112.850s 12114.385us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.870s 6104.354us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 447.610s 857.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 270.620s 12632.599us 1 1 100.00

Error Messages

   Test seed line log context