Simulation Results: rv_timer

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.69 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 93.24 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.500s 1409.428us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 37.550us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 28.259us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.140s 107.999us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.580s 26.020us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.870s 33.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 28.259us 1 1 100.00
rv_timer_csr_aliasing 0.580s 26.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.680s 318.814us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.730s 341.044us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 229.160s 652863.275us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 229.160s 652863.275us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.860s 5781.728us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 65.951us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 31.710us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.950s 515.152us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.950s 515.152us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 37.550us 1 1 100.00
rv_timer_csr_rw 0.590s 28.259us 1 1 100.00
rv_timer_csr_aliasing 0.580s 26.020us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 15.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 37.550us 1 1 100.00
rv_timer_csr_rw 0.590s 28.259us 1 1 100.00
rv_timer_csr_aliasing 0.580s 26.020us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 15.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 61.381us 1 1 100.00
rv_timer_tl_intg_err 1.030s 280.242us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.030s 280.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.680s 70.197us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.800s 189.961us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 15.410s 3452.530us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 96732149926226458492721433265813741759077176404908092955621061412524714357680 73
UVM_FATAL @ 70196642 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xef2c3b04) == 0x1
UVM_INFO @ 70196642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 15164414661461934277684846423472734009998654864465979268759169557264345141173 72
UVM_FATAL @ 318813758 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2a552304) == 0x1
UVM_INFO @ 318813758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 28583786881284444093363633090304328712748001770552190604190289413501204579286 73
UVM_ERROR @ 189960609 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 189960609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---