| V1 |
|
100.00% |
| V2 |
|
96.15% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 1.050s | 102.053us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 1.070s | 70.086us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 1.280s | 20.206us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 26.160s | 2703.110us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 16.000s | 347.618us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 2.070s | 30.290us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 1.280s | 20.206us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 16.000s | 347.618us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.670s | 11.022us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.420s | 225.103us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.780s | 55.718us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.900s | 1.635us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.830s | 5.065us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.680s | 70.760us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.680s | 70.760us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 5.840s | 8854.691us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.800s | 77.337us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 25.290s | 5594.749us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 8.610s | 20274.151us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 3.590s | 2253.424us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 3.590s | 2253.424us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 7.150s | 1706.230us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 7.150s | 1706.230us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 7.150s | 1706.230us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 7.150s | 1706.230us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 7.150s | 1706.230us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 5.640s | 2768.549us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 2.230s | 32.446us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 2.230s | 32.446us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 2.230s | 32.446us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 6.040s | 221.934us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 3.740s | 355.445us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 2.230s | 32.446us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 96.390s | 60236.554us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 8.010s | 1054.528us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 8.010s | 1054.528us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 1.050s | 102.053us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 15.840s | 10178.708us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 283.860s | 193770.517us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.830s | 29.804us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_device_intr_test | 0.760s | 16.416us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.670s | 179.649us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.670s | 179.649us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.070s | 70.086us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 1.280s | 20.206us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 16.000s | 347.618us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 3.330s | 3049.259us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.070s | 70.086us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 1.280s | 20.206us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 16.000s | 347.618us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 3.330s | 3049.259us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_device_tl_intg_err | 5.720s | 436.598us | 1 | 1 | 100.00 | |
| spi_device_sec_cm | 1.360s | 499.524us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_device_tl_intg_err | 5.720s | 436.598us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 31.640s | 31397.790us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | ||||
| spi_device_mem_parity | 52647854209848571464511359404370177434811734100603075331138326382009559580171 | 73 |
UVM_ERROR @ 1353424 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[46])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1353424 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1353424 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[942])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | ||||
| spi_device_ram_cfg | 35650888653386102499428098315649794545906174368286516558429977869933620611864 | 73 |
UVM_ERROR @ 2777600 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f1b8 [101111000110111000] vs 0x0 [0])
UVM_ERROR @ 2853600 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9708a0 [100101110000100010100000] vs 0x0 [0])
UVM_ERROR @ 2945600 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb745e5 [101101110100010111100101] vs 0x0 [0])
UVM_ERROR @ 2993600 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x199a38 [110011001101000111000] vs 0x0 [0])
UVM_ERROR @ 3090600 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2411e0 [1001000001000111100000] vs 0x0 [0])
|
|