Simulation Results: spi_host

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.23 %
  • code
  • 94.81 %
  • assert
  • 93.54 %
  • func
  • 88.33 %
  • block
  • 96.64 %
  • line
  • 98.47 %
  • branch
  • 92.95 %
  • toggle
  • 87.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 15.000s 1547.941us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 22.334us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 6.000s 15.971us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 497.692us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 48.037us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 81.909us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 6.000s 15.971us 1 1 100.00
spi_host_csr_aliasing 2.000s 48.037us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 47.795us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 17.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 20.913us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 81.953us 1 1 100.00
spi_host_error_cmd 2.000s 42.437us 1 1 100.00
spi_host_event 43.000s 3148.783us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 55.011us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 55.011us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 55.011us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 83.866us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 3.000s 110.284us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 55.011us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 55.011us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 15.000s 1547.941us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 15.000s 1547.941us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 53.725us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 176.520us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 37.000s 6121.529us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 74.658us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 81.953us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 54.385us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 26.653us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 221.462us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 221.462us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 22.334us 1 1 100.00
spi_host_csr_rw 6.000s 15.971us 1 1 100.00
spi_host_csr_aliasing 2.000s 48.037us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 246.765us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 22.334us 1 1 100.00
spi_host_csr_rw 6.000s 15.971us 1 1 100.00
spi_host_csr_aliasing 2.000s 48.037us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 246.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 178.823us 1 1 100.00
spi_host_sec_cm 1.000s 93.272us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 178.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 94.000s 7538.761us 1 1 100.00

Error Messages

   Test seed line log context