Simulation Results: sram_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.62 %
  • code
  • 85.64 %
  • assert
  • 95.55 %
  • func
  • 96.66 %
  • line
  • 96.43 %
  • branch
  • 93.32 %
  • cond
  • 90.58 %
  • toggle
  • 90.71 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 33.030s 1089.610us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 45.250us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.930s 25.800us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.390s 27.362us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 184.460us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.460s 1575.503us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.930s 25.800us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 184.460us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 105.930s 11955.388us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 67.880s 12103.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 533.230s 34755.373us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 257.770s 7390.370us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 799.860s 66960.920us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 778.260s 15220.697us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 52.540s 35800.915us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 336.220s 9484.387us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.890s 529.890us 1 1 100.00
sram_ctrl_partial_access_b2b 155.880s 18919.472us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 23.860s 842.024us 1 1 100.00
sram_ctrl_throughput_w_partial_write 41.760s 5052.065us 1 1 100.00
sram_ctrl_throughput_w_readback 10.450s 7306.268us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 208.820s 23396.001us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.470s 674.508us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2428.410s 140717.025us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.670s 182.839us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.370s 42.228us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.370s 42.228us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 45.250us 1 1 100.00
sram_ctrl_csr_rw 0.930s 25.800us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 184.460us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.950s 63.408us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 45.250us 1 1 100.00
sram_ctrl_csr_rw 0.930s 25.800us 1 1 100.00
sram_ctrl_csr_aliasing 0.870s 184.460us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.950s 63.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.070s 7694.202us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.070s 559.861us 1 1 100.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.070s 559.861us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 208.820s 23396.001us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 208.820s 23396.001us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.930s 25.800us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 336.220s 9484.387us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 336.220s 9484.387us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 336.220s 9484.387us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 52.540s 35800.915us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.090s 3324.786us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.070s 7694.202us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 5.350s 680.792us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 33.030s 1089.610us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 33.030s 1089.610us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 336.220s 9484.387us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 52.540s 35800.915us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 33.030s 1089.610us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.780s 3.957us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.020s 1761.440us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 52541167124904481522823990873996169162607824403354686344181992869960659307358 95
UVM_ERROR @ 680791774 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x43)
UVM_INFO @ 680791774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 46900286258235927418938136049187676495304206324660860176596944968999802970786 96
UVM_ERROR @ 3956736 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3956736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---