Simulation Results: sram_ctrl

 
18/12/2025 16:07:52 sha: fac57a7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.63 %
  • code
  • 93.24 %
  • assert
  • 95.65 %
  • func
  • 94.99 %
  • line
  • 98.23 %
  • branch
  • 95.45 %
  • cond
  • 91.55 %
  • toggle
  • 90.50 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 28.010s 305.267us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.760s 38.154us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.680s 35.647us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.760s 335.857us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 22.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 52.255us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.680s 35.647us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 22.137us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.120s 2699.495us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.390s 361.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 388.810s 15021.333us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 215.690s 2986.436us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 46.620s 1803.424us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 379.870s 10949.425us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.540s 1615.204us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 362.500s 5360.858us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.170s 210.303us 1 1 100.00
sram_ctrl_partial_access_b2b 237.690s 9051.862us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.270s 49.926us 1 1 100.00
sram_ctrl_throughput_w_partial_write 18.250s 338.164us 1 1 100.00
sram_ctrl_throughput_w_readback 57.620s 1033.926us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 741.820s 4360.923us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.060s 38.106us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2336.370s 524667.195us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.940s 21.658us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.070s 282.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.070s 282.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 38.154us 1 1 100.00
sram_ctrl_csr_rw 0.680s 35.647us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 22.137us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 72.669us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.760s 38.154us 1 1 100.00
sram_ctrl_csr_rw 0.680s 35.647us 1 1 100.00
sram_ctrl_csr_aliasing 0.760s 22.137us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.830s 72.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 204.501us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 2.110s 383.965us 1 1 100.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.110s 383.965us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 741.820s 4360.923us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 741.820s 4360.923us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.680s 35.647us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 362.500s 5360.858us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 362.500s 5360.858us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 362.500s 5360.858us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.540s 1615.204us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.210s 52.606us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.620s 204.501us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 1.160s 143.004us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 28.010s 305.267us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 28.010s 305.267us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 362.500s 5360.858us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.540s 1615.204us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 28.010s 305.267us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.690s 16.518us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 86.760s 1911.757us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 73587200052981904071535167933390642309274092108612410248224511929093668529532 95
UVM_ERROR @ 143003822 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x14) != exp (0x41)
UVM_INFO @ 143003822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 115783444838344842637980589482626107277343578693323400746872341045191478729268 97
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 6767597ps failed at 6767597ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 6839026ps failed at 6839026ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'