| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 0.850s | 127.274us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| uart_csr_hw_reset | 0.590s | 58.284us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 0.590s | 19.208us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 1.680s | 113.814us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| uart_csr_aliasing | 0.590s | 160.907us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 0.590s | 57.498us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| uart_csr_rw | 0.590s | 19.208us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.590s | 160.907us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 94.030s | 150948.977us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 0.850s | 127.274us | 1 | 1 | 100.00 | |
| uart_tx_rx | 94.030s | 150948.977us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 0.940s | 881.567us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 151.140s | 289097.790us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 94.030s | 150948.977us | 1 | 1 | 100.00 | |
| uart_intr | 0.940s | 881.567us | 1 | 1 | 100.00 | |
| fifo_full | 1 | 1 | 100.00 | |||
| uart_fifo_full | 17.580s | 31049.192us | 1 | 1 | 100.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 34.550s | 31156.770us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 55.150s | 145299.549us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 0.940s | 881.567us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 0.940s | 881.567us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 0.940s | 881.567us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 375.810s | 10588.797us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 0.880s | 2718.854us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 0.880s | 2718.854us | 1 | 1 | 100.00 | |
| rx_noise_filter | 0 | 1 | 0.00 | |||
| uart_noise_filter | 0.900s | 572.861us | 0 | 1 | 0.00 | |
| rx_start_bit_filter | 1 | 1 | 100.00 | |||
| uart_rx_start_bit_filter | 0.960s | 1494.266us | 1 | 1 | 100.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 6.280s | 6845.699us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 10.830s | 5506.657us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 185.440s | 88146.885us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| uart_stress_all | 951.880s | 510549.988us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 0.560s | 61.631us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 0.580s | 20.525us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.580s | 43.771us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.580s | 43.771us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.590s | 58.284us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.590s | 19.208us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.590s | 160.907us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.610s | 70.125us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.590s | 58.284us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.590s | 19.208us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.590s | 160.907us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.610s | 70.125us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 0.790s | 66.868us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 1.110s | 528.559us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 1.110s | 528.559us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 22.270s | 30800.976us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * | ||||
| uart_noise_filter | 97731069399254817195169956655255835243325650899677260631794431353884207825136 | 71 |
UVM_ERROR @ 41604938 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 41624169 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 41643400 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 221 [0xdd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 41662631 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 41681862 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 126 [0x7e]) reg name: uart_reg_block.rdata
|
|