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---\n","\n","\n"]},{"name":"i2c_target_stress_all_with_rand_reset","qual_name":"0.i2c_target_stress_all_with_rand_reset.50767730486296856036559669064680996788318688766991746028591357060331090037476","seed":50767730486296856036559669064680996788318688766991746028591357060331090037476,"line":101,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1028997913 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @ 1028997913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"i2c_host_mode_toggle","qual_name":"0.i2c_host_mode_toggle.94598646664077339314432285095216565981988472429395566854164110055036336816674","seed":94598646664077339314432285095216565981988472429395566854164110055036336816674,"line":81,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log","log_context":["UVM_ERROR @  14822222 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between\n","UVM_INFO @  14822222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in 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[*])":[{"name":"i2c_target_unexp_stop","qual_name":"0.i2c_target_unexp_stop.6746177231275525042664937172578139367958319978279654313355747512281536772016","seed":6746177231275525042664937172578139367958319978279654313355747512281536772016,"line":78,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log","log_context":["UVM_ERROR @  79341018 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 157 [0x9d]) \n","UVM_INFO @  79341018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!":[{"name":"i2c_target_hrst","qual_name":"0.i2c_target_hrst.71657162425604717917240340824765181724402761654906673997924816145735207467732","seed":71657162425604717917240340824765181724402761654906673997924816145735207467732,"line":79,"log_path":"/nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log","log_context":["UVM_FATAL @ 10082204709 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!\n","UVM_INFO @ 10082204709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding 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