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returned non-zero exit code":[{"name":"uart_fifo_full","qual_name":"0.uart_fifo_full.72316646592317602537572117601511656334745281982532096390758411085502656457875","seed":72316646592317602537572117601511656334745281982532096390758411085502656457875,"line":null,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log","log_context":["Chronologic VCS simulator copyright 1991-2023\n","Contains Synopsys proprietary information.\n","Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Mar 19 16:06 2026\n","Feature removed during lmreread, or wrong\n","SERVER line hostid.\n","Check your license file.\n","\n","Please contact VCS Customer Support at 1-800-VERILOG for more information.\n","\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255\n"]},{"name":"uart_rx_start_bit_filter","qual_name":"0.uart_rx_start_bit_filter.29182543215966566146455372886430094234154060656158678577223804534139325677390","seed":29182543215966566146455372886430094234154060656158678577223804534139325677390,"line":null,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_rx_start_bit_filter/latest/run.log","log_context":["Chronologic VCS simulator copyright 1991-2023\n","Contains Synopsys proprietary information.\n","Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Mar 19 16:06 2026\n","Feature removed during lmreread, or wrong\n","SERVER line hostid.\n","Check your license file.\n","\n","Please contact VCS Customer Support at 1-800-VERILOG for more information.\n","\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255\n"]},{"name":"uart_stress_all","qual_name":"0.uart_stress_all.66107591357897475702349191220378186639962043299619311705847342308821207504413","seed":66107591357897475702349191220378186639962043299619311705847342308821207504413,"line":null,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["Chronologic VCS simulator copyright 1991-2023\n","Contains Synopsys proprietary information.\n","Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Mar 19 16:06 2026\n","Feature removed during lmreread, or wrong\n","SERVER line hostid.\n","Check your license file.\n","\n","Please contact VCS Customer Support at 1-800-VERILOG for more information.\n","\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255\n"]},{"name":"uart_csr_hw_reset","qual_name":"0.uart_csr_hw_reset.38518294349975067732320104038870336662757246178951459931003644381626868183158","seed":38518294349975067732320104038870336662757246178951459931003644381626868183158,"line":null,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_hw_reset/latest/run.log","log_context":["Chronologic VCS simulator copyright 1991-2023\n","Contains Synopsys proprietary information.\n","Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Mar 19 16:06 2026\n","Feature removed during lmreread, or wrong\n","SERVER line hostid.\n","Check your license file.\n","\n","Please contact VCS Customer Support at 1-800-VERILOG for more information.\n","\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255\n"]},{"name":"uart_csr_aliasing","qual_name":"0.uart_csr_aliasing.32810826683457962396007417522204180642182733698344317863920775391298970696654","seed":32810826683457962396007417522204180642182733698344317863920775391298970696654,"line":null,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_aliasing/latest/run.log","log_context":["Chronologic VCS simulator copyright 1991-2023\n","Contains Synopsys proprietary information.\n","Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Mar 19 16:06 2026\n","Feature removed during lmreread, or wrong\n","SERVER line hostid.\n","Check your license file.\n","\n","Please contact VCS Customer Support at 1-800-VERILOG for more information.\n","\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255\n"]}],"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.63729761991434548592613212248410568260021505034452202631002865941047587806457","seed":63729761991434548592613212248410568260021505034452202631002865941047587806457,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  78909157 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @  78909157 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  78909157 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 273976055 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 273996673 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (76 [0x4c] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}]}},"passed":35,"total":46,"percent":76.08695652173913}