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---\n","\n","\n"]},{"name":"otp_ctrl_stress_all","qual_name":"0.otp_ctrl_stress_all.81890440841320293457258448106392521113578494108030766643284092369869751692700","seed":81890440841320293457258448106392521113578494108030766643284092369869751692700,"line":30937,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 24167450145 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch\n","UVM_INFO @ 24167450145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *":[{"name":"otp_ctrl_init_fail","qual_name":"0.otp_ctrl_init_fail.107776867049078320989180889304976152624897761305221653284933734643291866239367","seed":107776867049078320989180889304976152624897761305221653284933734643291866239367,"line":537,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest/run.log","log_context":["UVM_ERROR @  36801982 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0 \n","UVM_INFO @  36801982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_regwen","qual_name":"0.otp_ctrl_regwen.74902991744821871485021154127477717936915855259254219043005120899737275973","seed":74902991744821871485021154127477717936915855259254219043005120899737275973,"line":2756,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest/run.log","log_context":["UVM_ERROR @ 136064714 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0 \n","UVM_INFO @ 136064714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state":[{"name":"otp_ctrl_dai_lock","qual_name":"0.otp_ctrl_dai_lock.29156570664642805415879042738090713835513491675618544225638936415207194299071","seed":29156570664642805415879042738090713835513491675618544225638936415207194299071,"line":7124,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log","log_context":["UVM_ERROR @ 1597450276 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state\n","UVM_INFO @ 1597450276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*":[{"name":"otp_ctrl_macro_errs","qual_name":"0.otp_ctrl_macro_errs.78288821501253790300667045480545091420518225301987397346227337575543727732247","seed":78288821501253790300667045480545091420518225301987397346227337575543727732247,"line":2049,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest/run.log","log_context":["UVM_ERROR @ 189812340 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22\n","UVM_INFO @ 189812340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_test_access","qual_name":"0.otp_ctrl_test_access.29776921035059792131294359713275355398259766241735744313406039342325555547525","seed":29776921035059792131294359713275355398259766241735744313406039342325555547525,"line":2358,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log","log_context":["UVM_ERROR @ 121145569 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22\n","UVM_INFO @ 121145569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.20543455578259018097491333023361393529912916618746268533778433201380220333826","seed":20543455578259018097491333023361393529912916618746268533778433201380220333826,"line":94,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  31593724 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1\n","UVM_INFO @  31593724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":74,"total":94,"percent":78.72340425531915}