{"block":{"name":"clkmgr","variant":null,"commit":"bbe4dbf28bbfe815dcd11d723dc3e38635b46704","commit_short":"bbe4dbf","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/bbe4dbf28bbfe815dcd11d723dc3e38635b46704","revision_info":"GitHub Revision: [`bbe4dbf`](https://github.com/lowrisc/opentitan/tree/bbe4dbf28bbfe815dcd11d723dc3e38635b46704)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-03-24T16:05:07Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":0.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":5.43,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":0.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":2,"percent":50.0}},"passed":4,"total":8,"percent":50.0},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":0.76,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":0.77,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.12,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":0.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":0.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.63,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":0.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":0.72,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":0.75,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":1.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":1.78,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":0.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":4,"percent":50.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.01,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.97,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":0.61,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":4,"percent":50.0}},"passed":11,"total":19,"percent":57.89473684210526},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":3.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0},"clkmgr_tl_intg_err":{"max_time":0.66,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":0.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":0.66,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":0.73,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.63,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.18,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":1.51,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":3.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.59,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":3.95,"sim_time":0.0,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":9,"total":17,"percent":52.94117647058823},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":0.68,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":2.44,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":82.45,"branch":87.58,"condition_expression":79.63,"toggle":99.43,"fsm":0.0},"assertion":90.91,"functional":66.67},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.78816779213880524184849445308822915669592907925581437907779270967535125891393","seed":78816779213880524184849445308822915669592907925581437907779270967535125891393,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_ERROR @   5215200 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   5215200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.100598601767708516363602964877062637402995037554808189996310769125798944228400","seed":100598601767708516363602964877062637402995037554808189996310769125798944228400,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_ERROR @   3570572 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00\n","UVM_INFO @   3570572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.24385448130818609743941477371679721388661748471069057789727607799213789985586","seed":24385448130818609743941477371679721388661748471069057789727607799213789985586,"line":129,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 186801112 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @ 186801112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.3586446284780277883343735034057998744610737000761865161016810668794183421063","seed":3586446284780277883343735034057998744610737000761865161016810668794183421063,"line":77,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_ERROR @   7475048 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00\n","UVM_INFO @   7475048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.111614265006587682034894179551775848105771008787241667424248269576022163707615","seed":111614265006587682034894179551775848105771008787241667424248269576022163707615,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_ERROR @   4320536 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (9 [0x9] vs 3 [0x3]) reg name: clkmgr_reg_block.io_meas_ctrl_en\n","UVM_INFO @   4320536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.107521988176216098325690831293921432009123988567122862458732563728841452229556","seed":107521988176216098325690831293921432009123988567122862458732563728841452229556,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_ERROR @  22640341 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @  22640341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.40650683604268038924453434074200493981359894730938760258289504557256657106859","seed":40650683604268038924453434074200493981359894730938760258289504557256657106859,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_ERROR @   3122102 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   3122102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"0.clkmgr_csr_rw.38218727299318120032797318476745734911180699694689251280631794354363316754572","seed":38218727299318120032797318476745734911180699694689251280631794354363316754572,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log","log_context":["UVM_ERROR @   6724417 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   6724417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.10674722573374292571525001062559932860658764151931958131773060915032875920317","seed":10674722573374292571525001062559932860658764151931958131773060915032875920317,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   4637345 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1 \n","UVM_INFO @   4637345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.41239640328820900001809089203058839133685924673798597867417223485227922627472","seed":41239640328820900001809089203058839133685924673798597867417223485227922627472,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_ERROR @ 593967350 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0\n","UVM_INFO @ 593967350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.114345023421479054616170301125204408921338123042530908135941882718638929364574","seed":114345023421479054616170301125204408921338123042530908135941882718638929364574,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_ERROR @   7724516 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x63258564 read out mismatch\n","UVM_INFO @   7724516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":24,"total":46,"percent":52.17391304347826}