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---\n","\n","\n"]},{"name":"otp_ctrl_regwen","qual_name":"0.otp_ctrl_regwen.36893377729191336621652204601781188972388585047286528982234866805825153999486","seed":36893377729191336621652204601781188972388585047286528982234866805825153999486,"line":1790,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest/run.log","log_context":["UVM_ERROR @  51771153 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0 \n","UVM_INFO @  51771153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch":[{"name":"otp_ctrl_low_freq_read","qual_name":"0.otp_ctrl_low_freq_read.70029043348958428192010970833368523367023037768836486800670514194995103505205","seed":70029043348958428192010970833368523367023037768836486800670514194995103505205,"line":89,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest/run.log","log_context":["UVM_ERROR @ 21885553007 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch\n","UVM_INFO @ 21885553007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*":[{"name":"otp_ctrl_dai_lock","qual_name":"0.otp_ctrl_dai_lock.112531321681089035859000128514260995671842122426445241396282749160405525120020","seed":112531321681089035859000128514260995671842122426445241396282749160405525120020,"line":6991,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log","log_context":["UVM_ERROR @ 938281222 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22\n","UVM_INFO @ 938281222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_stress_all","qual_name":"0.otp_ctrl_stress_all.41201367002580915286510526989672458040216473934344187062221064343003868124890","seed":41201367002580915286510526989672458040216473934344187062221064343003868124890,"line":65134,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2327031367 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22\n","UVM_INFO @ 2327031367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*":[{"name":"otp_ctrl_check_fail","qual_name":"0.otp_ctrl_check_fail.90136704498359998922482818946675888403261782904843209735980530618874428948797","seed":90136704498359998922482818946675888403261782904843209735980530618874428948797,"line":12903,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log","log_context":["UVM_ERROR @ 332671266 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8192 [0x2000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0\n","UVM_INFO @ 332671266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.76328151771456731726273763583960119434465970716915156226917589802910901811438","seed":76328151771456731726273763583960119434465970716915156226917589802910901811438,"line":92,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 498749858 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1\n","UVM_INFO @ 498749858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":77,"total":94,"percent":81.91489361702128}