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---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"0.rv_dm_bad_sba_tl_access.48448239133854378927272095986013118630293124427600593464159496026563324682746","seed":48448239133854378927272095986013118630293124427600593464159496026563324682746,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"0.rv_dm_autoincr_sba_tl_access.36726387323018674063311180764711787217194724338221621121138389616695181130246","seed":36726387323018674063311180764711787217194724338221621121138389616695181130246,"line":86,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.7755998692039833997178673155305141045820776445630930147223028159636155650614","seed":7755998692039833997178673155305141045820776445630930147223028159636155650614,"line":77,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * 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---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.18103263374292682530487573076063613146144642299729411872487391204069373668707","seed":18103263374292682530487573076063613146144642299729411872487391204069373668707,"line":80,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1067114362 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1067114362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * 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