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mode":[{"name":"chip_sw_example_rom","qual_name":"0.chip_sw_example_rom.112367527414536388710553130397241651022319591688998617141756206325259981257245","seed":112367527414536388710553130397241651022319591688998617141756206325259981257245,"line":250,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_example_rom/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode\n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job returned non-zero exit code":[{"name":"chip_sw_example_manufacturer","qual_name":"0.chip_sw_example_manufacturer.43119383377761629027462220447163901340167415249153637517187648135943897168401","seed":43119383377761629027462220447163901340167415249153637517187648135943897168401,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_example_manufacturer/latest/run.log","log_context":["ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.506s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"0.chip_sw_data_integrity_escalation.6678435091507602532034013744595258708924788189333420677146923249349074923904","seed":6678435091507602532034013744595258708924788189333420677146923249349074923904,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.791s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.33271862360498022797474386904892986412459000019648506490627349248856200414805","seed":33271862360498022797474386904892986412459000019648506490627349248856200414805,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 12.235s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.98863369260282373899226184860989366900195007846856361351822940233100292737332","seed":98863369260282373899226184860989366900195007846856361351822940233100292737332,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 8.068s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"0.chip_sw_uart_tx_rx.18568165182136306112958158838457870703029886001447724697548451213559324404381","seed":18568165182136306112958158838457870703029886001447724697548451213559324404381,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_uart_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 14.717s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.109985983392292880755779788635785658582531571515168228429397447175997557910174","seed":109985983392292880755779788635785658582531571515168228429397447175997557910174,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 24.707s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"0.chip_sw_inject_scramble_seed.13505451004949755349112457782714556947631879444566455252339789592097339268211","seed":13505451004949755349112457782714556947631879444566455252339789592097339268211,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.188s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.80784105490998798941639356824211750444386487253230455447489319454757597978173","seed":80784105490998798941639356824211750444386487253230455447489319454757597978173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.327s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"0.chip_sw_uart_rand_baudrate.104673065964679324648889875204973093119426417040675897576186162513081016755538","seed":104673065964679324648889875204973093119426417040675897576186162513081016755538,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.385s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"0.chip_sw_uart_tx_rx_alt_clk_freq.66861348193599100713335837680812666712274058708492764915262528696291761147591","seed":66861348193599100713335837680812666712274058708492764915262528696291761147591,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 28.397s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"0.chip_sw_i2c_host_tx_rx.26086759698530161394582153413525860135870385167743322448938748171492933532581","seed":26086759698530161394582153413525860135870385167743322448938748171492933532581,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.680s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"0.chip_sw_i2c_device_tx_rx.7563823952806386948647774101848571917701601972552551162379074999768941609388","seed":7563823952806386948647774101848571917701601972552551162379074999768941609388,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.260s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"0.chip_sw_spi_device_tpm.60853431302708070878867084560764185749678183526957553591753216007244003493304","seed":60853431302708070878867084560764185749678183526957553591753216007244003493304,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 19.706s, Critical Path: 0.06s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"0.chip_sw_spi_host_tx_rx.66743869954625377979633779197820801276215166790786585224408306084338389769751","seed":66743869954625377979633779197820801276215166790786585224408306084338389769751,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 11.697s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"0.chip_sw_lc_ctrl_otp_hw_cfg.95797604546046306211715563110586757541870647454591802375868922346052286121403","seed":95797604546046306211715563110586757541870647454591802375868922346052286121403,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=133425) is running. Waiting for it to complete on the server (server_pid=66124)...\n","Another command (pid=131819) is running. Waiting for it to complete on the server (server_pid=66124)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.48510740407883040829889518993856048206124669243438152601733553021637593935319","seed":48510740407883040829889518993856048206124669243438152601733553021637593935319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.515s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"0.chip_sw_otp_ctrl_lc_signals_dev.4034561156470267578049022463425809394652526118438744482649116849735262546513","seed":4034561156470267578049022463425809394652526118438744482649116849735262546513,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.216s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"0.chip_sw_otp_ctrl_lc_signals_prod.111208917356312342657662359806931784281245279888104544057340342265322934507629","seed":111208917356312342657662359806931784281245279888104544057340342265322934507629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.656s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.32922547267159982415608445880929855272125188767972680703303710532055066388624","seed":32922547267159982415608445880929855272125188767972680703303710532055066388624,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.116s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"0.chip_sw_otp_ctrl_vendor_test_csr_access.34917910450406130571183880626156956718765613013941269017221851971679552334101","seed":34917910450406130571183880626156956718765613013941269017221851971679552334101,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.191s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_nvm_cnt","qual_name":"0.chip_sw_otp_ctrl_nvm_cnt.56631842759902224942674875499777109949692381645514756264245606368803156239082","seed":56631842759902224942674875499777109949692381645514756264245606368803156239082,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_nvm_cnt/latest/run.log","log_context":["Another command (pid=179834) is running. Waiting for it to complete on the server (server_pid=66124)...\n","Another command (pid=183170) is running. Waiting for it to complete on the server (server_pid=66124)...\n","Another command (pid=184778) is running. Waiting for it to complete on the server (server_pid=66124)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_sw_parts","qual_name":"0.chip_sw_otp_ctrl_sw_parts.24387533331106097556936606213294606301934461281645700510872661952383370490989","seed":24387533331106097556936606213294606301934461281645700510872661952383370490989,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_sw_parts/latest/run.log","log_context":["Another command (pid=175715) is running. Waiting for it to complete on the server (server_pid=66124)...\n","Another command (pid=176161) is running. Waiting for it to complete on the server (server_pid=66124)...\n","Another command (pid=174017) is running. Waiting for it to complete on the server (server_pid=66124)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.11988227291268671675738408935044189639568966055611976016066598159709595925927","seed":11988227291268671675738408935044189639568966055611976016066598159709595925927,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.225s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.114096220260606866846302988340943687833537167057266629484702825621518397038527","seed":114096220260606866846302988340943687833537167057266629484702825621518397038527,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 24.726s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.100816247309026683972689811400420704311863194245264468019261857716415724867247","seed":100816247309026683972689811400420704311863194245264468019261857716415724867247,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.751s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"0.chip_sw_lc_walkthrough_prodend.19456635155994344635582941537505892003051058700364060896376319895226394007716","seed":19456635155994344635582941537505892003051058700364060896376319895226394007716,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.564s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.634187825858683070964043849722699605080979150969325599096591827349442071906","seed":634187825858683070964043849722699605080979150969325599096591827349442071906,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.078s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.10019196460966663051456126981574071838295764879416906116605743575804299733116","seed":10019196460966663051456126981574071838295764879416906116605743575804299733116,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.697s, Critical Path: 0.08s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_main_power_glitch_reset.9226183049482061000536890662143357044454176260458202758444274008001977321799","seed":9226183049482061000536890662143357044454176260458202758444274008001977321799,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.056s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.25534457633890356315192769833185838275787005521064063910308492014872001065337","seed":25534457633890356315192769833185838275787005521064063910308492014872001065337,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 7.738s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.83102151804646172088559181311148355505626517892989455548897402547595813583131","seed":83102151804646172088559181311148355505626517892989455548897402547595813583131,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.108s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.33067209510776858459206535172508435297861053166540077939867356256956045818117","seed":33067209510776858459206535172508435297861053166540077939867356256956045818117,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.680s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"0.chip_sw_pwrmgr_sleep_disabled.54749993284539905546358726533818930835453304117089312033373222660254797393924","seed":54749993284539905546358726533818930835453304117089312033373222660254797393924,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.340s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"0.chip_sw_pwrmgr_wdog_reset.26974222947365534555481510799778909937721638769904641544365316666215393155234","seed":26974222947365534555481510799778909937721638769904641544365316666215393155234,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.364s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.83247315397032015375702250509576113027818167506563030494332075721289833796352","seed":83247315397032015375702250509576113027818167506563030494332075721289833796352,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_test/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"0.chip_sw_alert_handler_escalation.9207308377469892125353739227949238335023888379977172321634629720616704987422","seed":9207308377469892125353739227949238335023888379977172321634629720616704987422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.311s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.32287625947892356255011755120256476835063654933782116780110571201456128393094","seed":32287625947892356255011755120256476835063654933782116780110571201456128393094,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.709s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.95065132214393176119922144673782520641130566378220052037818526733306881872096","seed":95065132214393176119922144673782520641130566378220052037818526733306881872096,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.109732780992183919744310760457548891245636644897016146895872261796291845425600","seed":109732780992183919744310760457548891245636644897016146895872261796291845425600,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.342s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"0.chip_sw_alert_handler_lpg_clkoff.109755208366166237537767467247885227630101717940795024487629625031347835101459","seed":109755208366166237537767467247885227630101717940795024487629625031347835101459,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.304s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"0.chip_sw_alert_handler_lpg_reset_toggle.84298155436201893377181267814013678906379350877154790983551199764135939347835","seed":84298155436201893377181267814013678906379350877154790983551199764135939347835,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.296s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.51307876620189673413471511504794496690082838455544191735466004649702021198784","seed":51307876620189673413471511504794496690082838455544191735466004649702021198784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.317s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.5544832189911653239179917735742144400270574624971745267639790642204287543920","seed":5544832189911653239179917735742144400270574624971745267639790642204287543920,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.799s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"0.chip_sw_kmac_app_rom.49951846558068054541704968899375760021358653125700139360470922747627766764135","seed":49951846558068054541704968899375760021358653125700139360470922747627766764135,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_kmac_app_rom/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).\n","DEBUG: /nightly/current_run/opentitan/rules/autogen.bzl:536:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en.48570962456959413760186723911500584074816774118634800388501237041227416293289","seed":48570962456959413760186723911500584074816774118634800388501237041227416293289,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"0.chip_sw_sram_ctrl_execution_main.2606552462933716542335582760587757643291772926844244052774610751320088219424","seed":2606552462933716542335582760587757643291772926844244052774610751320088219424,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.322s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.53445600610595467211492796869015279804372074171759254552973446086220015507370","seed":53445600610595467211492796869015279804372074171759254552973446086220015507370,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_coremark/latest/run.log","log_context":["---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.12409642069781421095186509244651249330194015100048241813060625259465523807236","seed":12409642069781421095186509244651249330194015100048241813060625259465523807236,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.338s, Critical Path: 0.04s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.32732887590344144455127266505528559230532584038641164487304710170402578357840","seed":32732887590344144455127266505528559230532584038641164487304710170402578357840,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.286s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"0.chip_sw_ast_clk_outputs.106789090377398576057776932961767243914190351054393093079749385248857771519024","seed":106789090377398576057776932961767243914190351054393093079749385248857771519024,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.299s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"0.chip_sw_lc_ctrl_program_error.83379864833313006439200422551046432862268352260876818589388043142252275363598","seed":83379864833313006439200422551046432862268352260876818589388043142252275363598,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.296s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.112000708284665969628272773351609091116450679485788493935611235551802318036735","seed":112000708284665969628272773351609091116450679485788493935611235551802318036735,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.58621982663793073740632571326327262187191179082912987681836909354800085529908","seed":58621982663793073740632571326327262187191179082912987681836909354800085529908,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.113015550592433855410571538505297564034575146017733641990275730030678736649796","seed":113015550592433855410571538505297564034575146017733641990275730030678736649796,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.322s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"0.chip_sw_power_virus.44063761375009231982607310945128165318495414362168860609771571963434753829731","seed":44063761375009231982607310945128165318495414362168860609771571963434753829731,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.320s, Critical Path: 0.05s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"0.base_rom_e2e_smoke.24387275719072090497503833605370668617807596091028255902760028994296431802873","seed":24387275719072090497503833605370668617807596091028255902760028994296431802873,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 324, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 256, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"0.rom_e2e_smoke.74384020084544723150612062797918554961784425600266407198551251876490356038100","seed":74384020084544723150612062797918554961784425600266407198551251876490356038100,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_smoke/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.60948872579172658582909170659274095506699800467994730134389346126325822027141","seed":60948872579172658582909170659274095506699800467994730134389346126325822027141,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.97814428998951966697562909509461832752576872572522628951708516144100052223261","seed":97814428998951966697562909509461832752576872572522628951708516144100052223261,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_shutdown_output/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.60427338545730729213583989488521424341653986902244394630515302781874449117788","seed":60427338545730729213583989488521424341653986902244394630515302781874449117788,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.84556801126481671819324467844705560849583635250022323646310951788185030298545","seed":84556801126481671819324467844705560849583635250022323646310951788185030298545,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.12369401465542265185067897254215347878832636379411517675878992569450363716245","seed":12369401465542265185067897254215347878832636379411517675878992569450363716245,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.21421895870556844575492637184032202219992777708876683767814758235931094589101","seed":21421895870556844575492637184032202219992777708876683767814758235931094589101,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.13397809887465039026627014316179182038953380110717907842931673550834417531385","seed":13397809887465039026627014316179182038953380110717907842931673550834417531385,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.94325295388242985741126030794491245985838245225869519194108605492678715817216","seed":94325295388242985741126030794491245985838245225869519194108605492678715817216,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.28238008738481357964634369571867176621588016350953642106661947454937702630688","seed":28238008738481357964634369571867176621588016350953642106661947454937702630688,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.13352660025656308059081315972434772961253261599728696024168289934327234940519","seed":13352660025656308059081315972434772961253261599728696024168289934327234940519,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.86880667233409180955743634231271618373134716186458001932968731688016284452467","seed":86880667233409180955743634231271618373134716186458001932968731688016284452467,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.70654779867639339925248513520955377130857074125723103418119659754704638862896","seed":70654779867639339925248513520955377130857074125723103418119659754704638862896,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.106522600207158988565492807076334593390586316936358130674003851287514114747621","seed":106522600207158988565492807076334593390586316936358130674003851287514114747621,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.101214111201431126505390239333310392046152059872085379569000929454961686905903","seed":101214111201431126505390239333310392046152059872085379569000929454961686905903,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.22643846601904410750897409550225104075502639564517528139018530511274862565442","seed":22643846601904410750897409550225104075502639564517528139018530511274862565442,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3456969209581946481907094387967657671584508453087140155681378346511315065001","seed":3456969209581946481907094387967657671584508453087140155681378346511315065001,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.77153787699038453425262462922570455594037500772118074270418181987853695958510","seed":77153787699038453425262462922570455594037500772118074270418181987853695958510,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.58322102461589879087427794629600735100714102205387409654533346338274624684680","seed":58322102461589879087427794629600735100714102205387409654533346338274624684680,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.5376318867805625583682224536660523156739705067169849874784674691754247308534","seed":5376318867805625583682224536660523156739705067169849874784674691754247308534,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.92107401831095350750240630493187711848517415082609038098156411996658558988272","seed":92107401831095350750240630493187711848517415082609038098156411996658558988272,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.17480160421251812246789970709799915205061522926380558019438084508769582541902","seed":17480160421251812246789970709799915205061522926380558019438084508769582541902,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.51117049415961452460508194543908293730900853705497450776838574268153150242896","seed":51117049415961452460508194543908293730900853705497450776838574268153150242896,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.42624025089851094994636941035725640601218803044816930198407550274612387247939","seed":42624025089851094994636941035725640601218803044816930198407550274612387247939,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.75082991128876446456264911437444818712302915085431649381172489618545752365848","seed":75082991128876446456264911437444818712302915085431649381172489618545752365848,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.7953164668079841098772042896304496786632948690566666242022116597918889466558","seed":7953164668079841098772042896304496786632948690566666242022116597918889466558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.41819956738924247086747597471360346182833399860636443192227832306556637306740","seed":41819956738924247086747597471360346182833399860636443192227832306556637306740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.18362757307706267947499938004561909103051760298274565656089142699480838352510","seed":18362757307706267947499938004561909103051760298274565656089142699480838352510,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.18653255320605255294555027118388184791220474705812864809908589889450890063995","seed":18653255320605255294555027118388184791220474705812864809908589889450890063995,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.5437936466678535186688054939409794215788727297699707195605461196160982362659","seed":5437936466678535186688054939409794215788727297699707195605461196160982362659,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.53669822784292069536221379434621755670937567194090343419369516470733496978093","seed":53669822784292069536221379434621755670937567194090343419369516470733496978093,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=608767) is running. Waiting for it to complete on the server (server_pid=66124)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.17339456287121301419974203460750706966228747396361713356162347928333587701063","seed":17339456287121301419974203460750706966228747396361713356162347928333587701063,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=609031) is running. Waiting for it to complete on the server (server_pid=66124)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.22089835655135057652559363736731264904473531033749872012154041813629284071131","seed":22089835655135057652559363736731264904473531033749872012154041813629284071131,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.114953356367085952202842156828722214731300306759443401217186412775130361125455","seed":114953356367085952202842156828722214731300306759443401217186412775130361125455,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.35226676429860474619393398335921600257467090183646155077644575400518110003621","seed":35226676429860474619393398335921600257467090183646155077644575400518110003621,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.86420202815203508919102254242003196959304616341681521202911645892532247439189","seed":86420202815203508919102254242003196959304616341681521202911645892532247439189,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.64909504471335549041779985660059371295362423719371686630731465809903464534766","seed":64909504471335549041779985660059371295362423719371686630731465809903464534766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.95332969366626479086001947451901801594468188936352926818800777276269095483794","seed":95332969366626479086001947451901801594468188936352926818800777276269095483794,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.40900143804156702095795314859966180986284789907793331826537648727429633184813","seed":40900143804156702095795314859966180986284789907793331826537648727429633184813,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.85922015259213176535091159837672657030383420003433305787226193883576400562947","seed":85922015259213176535091159837672657030383420003433305787226193883576400562947,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.96125728835015769572506368681369806854944058628919343291514914143376396426717","seed":96125728835015769572506368681369806854944058628919343291514914143376396426717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.95321020274061208733462514990591379888683150937582625055011877074998508798109","seed":95321020274061208733462514990591379888683150937582625055011877074998508798109,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.44630194116240071666750641465633246804583556587766183981807779053258023521989","seed":44630194116240071666750641465633246804583556587766183981807779053258023521989,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.15932138176228484851614804700048318156351138003912818748442048315024456891179","seed":15932138176228484851614804700048318156351138003912818748442048315024456891179,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"0.rom_e2e_static_critical.99064698314098280013653882625640441748923069187518268520433300164079745093527","seed":99064698314098280013653882625640441748923069187518268520433300164079745093527,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_static_critical/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.19259325352289442568608382793942080609541412189099711660139271228091332552067","seed":19259325352289442568608382793942080609541412189099711660139271228091332552067,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.1112949958817768691091567101962037032366452232280268662254033922958860453854","seed":1112949958817768691091567101962037032366452232280268662254033922958860453854,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_invalid_meas.76048253763103805231219513489773493899720225361926781516600538284326493919225","seed":76048253763103805231219513489773493899720225361926781516600538284326493919225,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.13783258111136900446762983158997189556473146209858044062263503590888011514531","seed":13783258111136900446762983158997189556473146209858044062263503590888011514531,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.42918351766423110465903762007303522558142722497065498755173207821869871260691","seed":42918351766423110465903762007303522558142722497065498755173207821869871260691,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_otbn.81182060094601032462137849575799817837911406842797055087867505667691942574535","seed":81182060094601032462137849575799817837911406842797055087867505667691942574535,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_sw.18402360549391171354261754538698116788101533238762282291290118588644596794015","seed":18402360549391171354261754538698116788101533238762282291290118588644596794015,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_otbn.45547352140341468762457454069611854626618817201735733725092144809408877071119","seed":45547352140341468762457454069611854626618817201735733725092144809408877071119,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_sw.106046063871154779250176163477929947025136069919100914324861552617541627293304","seed":106046063871154779250176163477929947025136069919100914324861552617541627293304,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_otbn.20834513196372799139385861757770980455524266641579129426750675289430319792816","seed":20834513196372799139385861757770980455524266641579129426750675289430319792816,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_sw.50206199909231992893592999523830829995761878444935678295379537052129655879360","seed":50206199909231992893592999523830829995761878444935678295379537052129655879360,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_otbn.41017886679584312597340533693932441210973651359925240118584599535852781767806","seed":41017886679584312597340533693932441210973651359925240118584599535852781767806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_sw.100467854390240858166832435658942599324951650860789909797052566613662129009325","seed":100467854390240858166832435658942599324951650860789909797052566613662129009325,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.66618844573002677855745331292907554543834943483983575626439561464390644881280","seed":66618844573002677855745331292907554543834943483983575626439561464390644881280,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.58793751379163202668414586229729892056352455114225646441119838693309951604504","seed":58793751379163202668414586229729892056352455114225646441119838693309951604504,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.97088103580021781689315721564174221635724766329128145717211928848676521203567","seed":97088103580021781689315721564174221635724766329128145717211928848676521203567,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"0.chip_sw_uart_smoketest_signed.111114836753073958757459326004907591871749128270176182851206063566551356436465","seed":111114836753073958757459326004907591871749128270176182851206063566551356436465,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.69566094078142671394213617534672700385357242188370309951141217637805166350985","seed":69566094078142671394213617534672700385357242188370309951141217637805166350985,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.984s, Critical Path: 0.08s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.82163602920491849845421070536609937778868606464044418025142664910114857027070","seed":82163602920491849845421070536609937778868606464044418025142664910114857027070,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.83499148714128107950134231749426154065942933745298389614830001313916176354279","seed":83499148714128107950134231749426154065942933745298389614830001313916176354279,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"chip_sw_spi_device_pass_through","qual_name":"0.chip_sw_spi_device_pass_through.3135279758884410776957596835320705808982124220658618205723471570628187184027","seed":3135279758884410776957596835320705808982124220658618205723471570628187184027,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_spi_device_pass_through/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"0.chip_sw_rom_ctrl_integrity_check.47609043223296787853167577550496578165735013559008494232116519989186586085352","seed":47609043223296787853167577550496578165735013559008494232116519989186586085352,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["Job timed out after 60 minutes"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.83204999015721567405230643676572097103140111092329892622692515889893539188478","seed":83204999015721567405230643676572097103140111092329892622692515889893539188478,"line":302,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_ERROR @ 277.504500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty\n","UVM_INFO @ 277.504500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_lc_ctrl_*/rtl/lc_ctrl.sv,885): (time * NS) Assertion LcInitDoneSticky_A has failed (* cycles, starting * NS)":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.69669518195119605788084767805082776019611864514815106297447214190579531512330","seed":69669518195119605788084767805082776019611864514815106297447214190579531512330,"line":301,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl.sv,885): (time 180166 NS) Assertion tb.dut.top_darjeeling.u_lc_ctrl.LcInitDoneSticky_A has failed (2 cycles, starting 180162 NS)\n","UVM_ERROR @ 180.166000 us: (lc_ctrl.sv:885) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 180.166000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_rstmgr_alert_info","qual_name":"0.chip_sw_rstmgr_alert_info.64937405003200356068860394190609013710175807873539234676613586198346778006690","seed":64937405003200356068860394190609013710175807873539234676613586198346778006690,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_ERROR @ 334.687500 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size\n","UVM_INFO @ 334.687500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_*/pwrmgr_rstreqs_sva_if.sv,59): (time * NS) Assertion HwResetOff_A has failed (* cycles, starting * NS)":[{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.9382188629275199587182012779486806331622672493595784938616420569694852461073","seed":9382188629275199587182012779486806331622672493595784938616420569694852461073,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 413080 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 406680 NS)\n","UVM_ERROR @ 413.080000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 413.080000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"0.chip_sw_clkmgr_off_aes_trans.3111831033702200658641451250868730774456911197177741038370317231720307672025","seed":3111831033702200658641451250868730774456911197177741038370317231720307672025,"line":296,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184488 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178088 NS)\n","UVM_ERROR @ 184.488000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 184.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"0.chip_sw_clkmgr_off_hmac_trans.107758527422788421214009310271115556816940921863245649991387818860397036887758","seed":107758527422788421214009310271115556816940921863245649991387818860397036887758,"line":296,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184536 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178136 NS)\n","UVM_ERROR @ 184.536000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 184.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"0.chip_sw_clkmgr_off_kmac_trans.66740182148193893447446778065802435714704665262705655591559504083761924661632","seed":66740182148193893447446778065802435714704665262705655591559504083761924661632,"line":296,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184488 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178088 NS)\n","UVM_ERROR @ 184.488000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 184.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"0.chip_sw_clkmgr_off_otbn_trans.86118604178482406780143030375282669219869074121188025729723135825094442441822","seed":86118604178482406780143030375282669219869074121188025729723135825094442441822,"line":296,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_darjeeling_dv_pwrmgr_sva_0.1/pwrmgr_rstreqs_sva_if.sv,59): (time 184536 NS) Assertion tb.dut.top_darjeeling.pwrmgr_rstreqs_sva_if.gen_hw_resets[0].HwResetOff_A has failed (401 cycles, starting 178136 NS)\n","UVM_ERROR @ 184.536000 us: (pwrmgr_rstreqs_sva_if.sv:59) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 184.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:58) [chip_env_pkg::chip_sw_soc_proxy_smoke_vseq.body] Resets did not complete within required time!":[{"name":"chip_sw_soc_proxy_smoketest","qual_name":"0.chip_sw_soc_proxy_smoketest.33187899002951503081357554555619744539200719947743754022051493736219318972069","seed":33187899002951503081357554555619744539200719947743754022051493736219318972069,"line":293,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_ERROR @ 157.320000 us: (chip_sw_soc_proxy_smoke_vseq.sv:58) [chip_env_pkg::chip_sw_soc_proxy_smoke_vseq.body] Resets did not complete within required time!\n","UVM_INFO @ 157.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *":[{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"0.chip_sw_soc_proxy_external_wakeup.75689548187690009982500171348020268340811577390117838822589826312975065399275","seed":75689548187690009982500171348020268340811577390117838822589826312975065399275,"line":291,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_ERROR @ 157.675500 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3\n","UVM_INFO @ 157.675500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec":[{"name":"chip_sw_aon_timer_irq","qual_name":"0.chip_sw_aon_timer_irq.87160428647058559062726172395126371623052445090043521785171211871564566189069","seed":87160428647058559062726172395126371623052445090043521785171211871564566189069,"line":292,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_ERROR @ 606.607500 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4481 usec which is not in the range 409 usec and 466 usec\n","UVM_INFO @ 606.607500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds":[{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.108393573940007936949483912356824819065115034529430776128622447513813331763943","seed":108393573940007936949483912356824819065115034529430776128622447513813331763943,"line":293,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 183.196500 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds\n","UVM_INFO @ 183.196500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\"":[{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en.78955587193335060068100793791197256747846605526708258288252612400477394429926","seed":78955587193335060068100793791197256747846605526708258288252612400477394429926,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"0.chip_sw_aes_enc_jitter_en.28484550940484016328318535392473615741824230783351389960604686962695320539787","seed":28484550940484016328318535392473615741824230783351389960604686962695320539787,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"0.chip_sw_hmac_enc_jitter_en.112670510519373319222832415857039090022811890950542931544969459322902957776761","seed":112670510519373319222832415857039090022811890950542931544969459322902957776761,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en.8698929397107934640476802243953299997155360444831148794048796065930857745688","seed":8698929397107934640476802243953299997155360444831148794048796065930857745688,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en.108530124079725072506120023889188875828935648087899149820604033811011444827386","seed":108530124079725072506120023889188875828935648087899149820604033811011444827386,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.60708027060490251984847675053381165559772333712109180045186706701573277570943","seed":60708027060490251984847675053381165559772333712109180045186706701573277570943,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_aes_enc_jitter_en_reduced_freq.64239779387186525255940402810802503019997142216770461648348543692378320197162","seed":64239779387186525255940402810802503019997142216770461648348543692378320197162,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_hmac_enc_jitter_en_reduced_freq.110283923029724649339651387219194407610154434144030192114335254764404607431438","seed":110283923029724649339651387219194407610154434144030192114335254764404607431438,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.55153478506523440845119542330611077170159848482327617409666387308058353396660","seed":55153478506523440845119542330611077170159848482327617409666387308058353396660,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.58745100780313694282653228152520592973950368423359639948563058977783596921755","seed":58745100780313694282653228152520592973950368423359639948563058977783596921755,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.13791551475399227350377131663072634700827422605156894229495523614739673264984","seed":13791551475399227350377131663072634700827422605156894229495523614739673264984,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.85091392688955068386949672718431219352998556071236615494914343182913321114918","seed":85091392688955068386949672718431219352998556071236615494914343182913321114918,"line":284,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unmblk2] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\" \n","UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired":[{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"0.chip_sw_rv_core_ibex_nmi_irq.92771717456479281722247979159693618531275567774399285064272693826661350117509","seed":92771717456479281722247979159693618531275567774399285064272693826661350117509,"line":294,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_ERROR @ 271.149500 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired\n","UVM_INFO @ 271.149500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP":[{"name":"chip_sw_keymgr_dpe_key_derivation","qual_name":"0.chip_sw_keymgr_dpe_key_derivation.54844794493976692834369563434082036071591329005266265154527661303926994491097","seed":54844794493976692834369563434082036071591329005266265154527661303926994491097,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log","log_context":["UVM_ERROR @ 305.127500 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11314292908807006366441093420157506913726939817332328017525268695597507971850397323915767687608665636395409254420125343004103608610759443931813699165445212 [0xd8071c9aaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35e51ac6b7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.127500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_prod","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_prod.54765330493492577141050900543982638123084457414713425912303146996747851502513","seed":54765330493492577141050900543982638123084457414713425912303146996747851502513,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log","log_context":["UVM_ERROR @ 305.147500 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (3323785836578353055518553943931850673725517346309757466955698516745057447577524226876069176494307853956272542873252058804357435722716658849036080026836060 [0x3f7653a5aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3b920e3547f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP\n","UVM_INFO @ 305.147500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.47776233798412805504911828123906474267600522843483669483801348649466265572390","seed":47776233798412805504911828123906474267600522843483669483801348649466265572390,"line":5922,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_ERROR @ 117.002500 us: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@180656) { a_addr: 'h30480000  a_data: 'h1216af1f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h0  a_user: 'h26916  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"}.\n","UVM_INFO @ 117.002500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.76205731005119095464409941477825448893860845214868959246274667192013163718608","seed":76205731005119095464409941477825448893860845214868959246274667192013163718608,"line":5922,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_jtag_mem_access/latest/run.log","log_context":["UVM_ERROR @ 116.987500 us: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@180658) { a_addr: 'h30480000  a_data: 'h6302c075  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h0  a_user: 'h26913  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unmapped address\"}.\n","UVM_INFO @ 116.987500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:696) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.18558636109526147970039857247823736301532374110394733554302166113188271527370","seed":18558636109526147970039857247823736301532374110394733554302166113188271527370,"line":294,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_FATAL @ 123.717000 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:696) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.\n","UVM_INFO @ 123.717000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *":[{"name":"chip_sw_dma_abort","qual_name":"0.chip_sw_dma_abort.27010445752523441745305816806527733665244743598733047291706910254927350890578","seed":27010445752523441745305816806527733665244743598733047291706910254927350890578,"line":297,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_dma_abort/latest/run.log","log_context":["UVM_ERROR @ 212.032500 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1\n","UVM_INFO @ 212.032500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_*/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_*/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.":[{"name":"xbar_smoke","qual_name":"0.xbar_smoke.8675986959601360661266836433391091117529811100290700209185104397658506531522","seed":8675986959601360661266836433391091117529811100290700209185104397658506531522,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_smoke/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.49025697109432420772646044385954502085237892195302020885206673977556860819074","seed":49025697109432420772646044385954502085237892195302020885206673977556860819074,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_smoke_zero_delays/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.15005802458661714180589035882360599756546501596008432764898545686770019739818","seed":15005802458661714180589035882360599756546501596008432764898545686770019739818,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_smoke_large_delays/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.1588133506319308353302388063789132355930528862612515485993379822193764351358","seed":1588133506319308353302388063789132355930528862612515485993379822193764351358,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.58207784491208213875381643434741743344763825114858057314449913863351291890356","seed":58207784491208213875381643434741743344763825114858057314449913863351291890356,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_random/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.91685239728548716929002259626749497906852056848945876163484013724489848633833","seed":91685239728548716929002259626749497906852056848945876163484013724489848633833,"line":465,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_random_zero_delays/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.71124154269263835008815891982739961706131170524000491222977962524369775742997","seed":71124154269263835008815891982739961706131170524000491222977962524369775742997,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_random_large_delays/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.33147201706746998540521833122462405404194106136490704813950994808156522770687","seed":33147201706746998540521833122462405404194106136490704813950994808156522770687,"line":360,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_random_slow_rsp/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.41169708514169005837246978271662703931983534945503258734235925124107761077784","seed":41169708514169005837246978271662703931983534945503258734235925124107761077784,"line":345,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_access_same_device/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.59680187399552456296412912356572753168169381131022030749104524335797365094950","seed":59680187399552456296412912356572753168169381131022030749104524335797365094950,"line":405,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.55491904112761362438674706866682897223531749910713867937124658076805683934454","seed":55491904112761362438674706866682897223531749910713867937124658076805683934454,"line":2730,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_same_source/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.58608976127370445063615274723206585848711741556986611497350728790680065588363","seed":58608976127370445063615274723206585848711741556986611497350728790680065588363,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_error_random/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.60075054197892751756926023349205266044256711457449766446611401452470443791617","seed":60075054197892751756926023349205266044256711457449766446611401452470443791617,"line":420,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_unmapped_addr/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.3587076965340575540648083035376922349060500965504801290672267708457433550952","seed":3587076965340575540648083035376922349060500965504801290672267708457433550952,"line":345,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.47504971099193656305471270087596138027224150822937275168898955151128654565870","seed":47504971099193656305471270087596138027224150822937275168898955151128654565870,"line":1818,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_stress_all/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.99558625093875657649544597427238575636244313744194079552778672498484202603228","seed":99558625093875657649544597427238575636244313744194079552778672498484202603228,"line":27106,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.57116765278496044332896251792701714986681768072484813216512576608985602728603","seed":57116765278496044332896251792701714986681768072484813216512576608985602728603,"line":2223,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_stress_all_with_error/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.92983561164951594237860504948275272230862831568050315685668087837659044262582","seed":92983561164951594237860504948275272230862831568050315685668087837659044262582,"line":15862,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'dma__host' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'dma__host' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx0__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx0__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx1__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx1__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx2__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx2__sram' in the same scope was earlier saved to the database.\n","xmsim: *E,CGNCTN: Coverage dumping for covergroup instance variable max_delay_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv:25) with 'mbx3__sram' as instance name failed, as another covergroup instance variable bit_toggle_cg (/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_dv_lib_0/bit_toggle_cg_wrap.sv:30) with the same instance name 'mbx3__sram' in the same scope was earlier saved to the database.\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.106759992390302476455306710899361649422220964801163641362900472324527570958435","seed":106759992390302476455306710899361649422220964801163641362900472324527570958435,"line":201,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 117.951500 us: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_soc_mbx_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@171860) { a_addr: 'h1465210  a_data: 'he3dcd959  a_mask: 'h7  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h1  a_user: 'h27394  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"}.\n","UVM_INFO @ 117.951500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}]}},"passed":64,"total":242,"percent":26.446280991735538}