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rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"}.\n","UVM_INFO @   3016874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"mbx_csr_mem_rw_with_rand_reset","qual_name":"0.mbx_csr_mem_rw_with_rand_reset.24765406974019045205150526625715447124006004147858888179353977976371679051253","seed":24765406974019045205150526625715447124006004147858888179353977976371679051253,"line":86,"log_path":"/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @   8568063 ps: (cip_base_scoreboard.sv:582) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted 1, but saw 0).\n"," TL item was: req: (cip_tl_seq_item@17625) { a_addr: 'h43567530  a_data: 'h38578500  a_mask: 'h8  a_size: 'h2  a_param: 'h0  a_source: 'h4f  a_opcode: 'h1  a_user: 'h252a4  d_param: 'h0  d_source: 'h4f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Unsupported partial write\"}.\n","UVM_INFO @   8568063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}]}},"passed":13,"total":16,"percent":81.25}