{"block":{"name":"sram_ctrl","variant":"ret","commit":"08f559e037721d6bccf5f4afd0ab3fb272ce2faf","commit_short":"08f559e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/08f559e037721d6bccf5f4afd0ab3fb272ce2faf","revision_info":"GitHub Revision: [`08f559e`](https://github.com/lowrisc/opentitan/tree/08f559e037721d6bccf5f4afd0ab3fb272ce2faf)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-02T16:07:25Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":58.0,"sim_time":680.900067,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.101973,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":28.167783,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":2.0,"sim_time":97.613553,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":94.177582,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":98.811652,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":28.167783,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":94.177582,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":9.0,"sim_time":1234.550835,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":6.0,"sim_time":161.409109,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":579.0,"sim_time":72401.889507,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":174.0,"sim_time":16552.477333,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":22.0,"sim_time":7289.477062,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":163.0,"sim_time":3047.4594300000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":1784.6721839999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":140.0,"sim_time":23690.620948,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":12.0,"sim_time":1648.298178,"passed":1,"total":1,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":230.0,"sim_time":15458.478894,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":2.0,"sim_time":36.850623,"passed":0,"total":1,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":8.0,"sim_time":90.56667900000001,"passed":1,"total":1,"percent":100.0},"sram_ctrl_throughput_w_readback":{"max_time":1.0,"sim_time":45.290635,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":3,"percent":33.333333333333336},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":107.0,"sim_time":728.26092,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":2.0,"sim_time":181.834382,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":2926.0,"sim_time":51348.867621,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":1.0,"sim_time":13.484936,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.0,"sim_time":87.950902,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":3.0,"sim_time":87.950902,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.101973,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":28.167783,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":94.177582,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":35.624742,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":1.0,"sim_time":37.101973,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":28.167783,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":94.177582,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":35.624742,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":18,"total":20,"percent":90.0},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":3.0,"sim_time":439.800608,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0},"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":351.33997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":2,"percent":50.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":2.0,"sim_time":351.33997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":107.0,"sim_time":728.26092,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":107.0,"sim_time":728.26092,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":1.0,"sim_time":28.167783,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":140.0,"sim_time":23690.620948,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":140.0,"sim_time":23690.620948,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":140.0,"sim_time":23690.620948,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":1784.6721839999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":1.0,"sim_time":61.306427000000006,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":3.0,"sim_time":439.800608,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":2.0,"sim_time":131.011879,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":58.0,"sim_time":680.900067,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":58.0,"sim_time":680.900067,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":140.0,"sim_time":23690.620948,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":5.0,"sim_time":1784.6721839999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":58.0,"sim_time":680.900067,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":2.0,"sim_time":1.565347,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":7,"total":10,"percent":70.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":12.0,"sim_time":747.588807,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"coverage":{"code":{"block":92.31,"line_statement":93.12,"branch":86.11,"condition_expression":null,"toggle":82.61,"fsm":66.67},"assertion":95.22,"functional":93.0},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.71498325420533932785279155271860252579793387229828137781870152142832162051735","seed":71498325420533932785279155271860252579793387229828137781870152142832162051735,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_FATAL @  36850623 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  36850623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.107274975758547665647933919507805483691232704529547954532838073398903434359410","seed":107274975758547665647933919507805483691232704529547954532838073398903434359410,"line":102,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_FATAL @  45290635 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2;         mask dist {'1 :/ 100 - partial_access_pct,                    [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! \n","UVM_INFO @  45290635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)":[{"name":"sram_ctrl_readback_err","qual_name":"0.sram_ctrl_readback_err.6837489573460271115752038704960811311869138902038077447446309819194333852876","seed":6837489573460271115752038704960811311869138902038077447446309819194333852876,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_readback_err/latest/run.log","log_context":["UVM_ERROR @ 131011879 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x37)\n","UVM_INFO @ 131011879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_*/rtl/tlul_adapter_sram.sv,636): Assertion rvalidHighReqFifoEmpty has failed":[{"name":"sram_ctrl_mubi_enc_err","qual_name":"0.sram_ctrl_mubi_enc_err.52840079670086716931049541869867638735619690969204728475334210319417478719470","seed":52840079670086716931049541869867638735619690969204728475334210319417478719470,"line":89,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv,636): (time 61306427 PS) Assertion tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.rvalidHighReqFifoEmpty has failed \n","UVM_ERROR @  61306427 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty\n","UVM_INFO @  61306427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_*/rtl/tlul_assert.sv,293): Assertion respMustHaveReq_A has failed":[{"name":"sram_ctrl_sec_cm","qual_name":"0.sram_ctrl_sec_cm.18684057450193041085343808344873272913254247143303194385748440998266060080712","seed":18684057450193041085343808344873272913254247143303194385748440998266060080712,"line":89,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_sec_cm/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,293): (time 841365 PS) Assertion tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A has failed \n","UVM_ERROR @   1565347 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 \n","UVM_INFO @   1565347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":26,"total":31,"percent":83.87096774193549}