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---\n","\n","\n"]},{"name":"rv_timer_random_reset","qual_name":"0.rv_timer_random_reset.32109207678178379018559214877445224773532947555989616279452499399066791653364","seed":32109207678178379018559214877445224773532947555989616279452499399066791653364,"line":84,"log_path":"/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_random_reset/latest/run.log","log_context":["UVM_FATAL @ 100237799 ps: (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcf10f104) == 0x1\n","UVM_INFO @ 100237799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * 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