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---\n","\n","\n"]},{"name":"rv_dm_bad_sba_tl_access","qual_name":"0.rv_dm_bad_sba_tl_access.108018124731731930687155331925889801704950004067541008702396488151250467187605","seed":108018124731731930687155331925889801704950004067541008702396488151250467187605,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_autoincr_sba_tl_access","qual_name":"0.rv_dm_autoincr_sba_tl_access.32630298670066496545008064886757794708632535916827742804988839035348054214931","seed":32630298670066496545008064886757794708632535916827742804988839035348054214931,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.27669689452065731558282810920328421969850602991510995540989239878863369602512","seed":27669689452065731558282810920328421969850602991510995540989239878863369602512,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*])":[{"name":"rv_dm_mem_tl_access_resuming","qual_name":"0.rv_dm_mem_tl_access_resuming.46254274475908143602269834355110593713376005869428830233903636026135144155458","seed":46254274475908143602269834355110593713376005869428830233903636026135144155458,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest/run.log","log_context":["UVM_ERROR @ 376688141 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 376688141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.73884295476279587015053879730159656592262945322200878267642116420288683660446","seed":73884295476279587015053879730159656592262945322200878267642116420288683660446,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all/latest/run.log","log_context":["UVM_ERROR @ 888300615 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 888300615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.15332144574131624828588448721444129211694388352777069922388449111611027211486","seed":15332144574131624828588448721444129211694388352777069922388449111611027211486,"line":103,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 121513293 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 1'b1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 121513293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*])":[{"name":"rv_dm_hart_unavail","qual_name":"0.rv_dm_hart_unavail.80843010357407773227950215677391479698906889087775551818051024997850335976178","seed":80843010357407773227950215677391479698906889087775551818051024997850335976178,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest/run.log","log_context":["UVM_ERROR @ 348548795 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 348548795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])":[{"name":"rv_dm_jtag_dmi_debug_disabled","qual_name":"0.rv_dm_jtag_dmi_debug_disabled.35942359879141671671570081199561654800663549519103114634842563622864430938077","seed":35942359879141671671570081199561654800663549519103114634842563622864430938077,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 282653403 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2811579674 [0xa7954d1a] vs 0 [0x0]) \n","UVM_INFO @ 282653403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":43,"total":53,"percent":81.13207547169812}