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uart_reg_block.rdata\n","UVM_ERROR @ 27342244933 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 27342286600 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (76 [0x4c] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"0.uart_stress_all.67158898782633311800517691240703876375749909941602178307346881389027518073879","seed":67158898782633311800517691240703876375749909941602178307346881389027518073879,"line":114,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 322068022374 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 322068062374 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 322068102374 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (128 [0x80] vs 215 [0xd7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 322203382374 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 322203422374 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}]}},"passed":25,"total":27,"percent":92.5925925925926}