{"block":{"name":"dma","variant":null,"commit":"c46226fa58eadd75dd17646cf36d76b333ab8dd7","commit_short":"c46226f","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/c46226fa58eadd75dd17646cf36d76b333ab8dd7","revision_info":"GitHub Revision: [`c46226f`](https://github.com/lowrisc/opentitan/tree/c46226fa58eadd75dd17646cf36d76b333ab8dd7)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-04T19:40:26Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/dma/data/dma_testplan.html","stages":{"V1":{"testpoints":{"dma_memory_smoke":{"tests":{"dma_memory_smoke":{"max_time":5.0,"sim_time":3878.603235,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_smoke":{"tests":{"dma_handshake_smoke":{"max_time":5.0,"sim_time":278.16267700000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_generic_smoke":{"tests":{"dma_generic_smoke":{"max_time":5.0,"sim_time":599.2439320000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":14.61341,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"dma_csr_rw":{"max_time":1.0,"sim_time":27.824643000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"dma_csr_bit_bash":{"max_time":10.0,"sim_time":3587.559105,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"dma_csr_aliasing":{"max_time":6.0,"sim_time":442.701655,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"dma_csr_mem_rw_with_rand_reset":{"max_time":1.0,"sim_time":214.740446,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"dma_csr_rw":{"max_time":1.0,"sim_time":27.824643000000002,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":6.0,"sim_time":442.701655,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"V2":{"testpoints":{"dma_memory_region_lock":{"tests":{"dma_memory_region_lock":{"max_time":43.0,"sim_time":10610.498678,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_memory_tl_error":{"tests":{"dma_memory_stress":{"max_time":155.0,"sim_time":60424.376537000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_tl_error":{"tests":{"dma_handshake_stress":{"max_time":638.0,"sim_time":95742.614281,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_stress":{"tests":{"dma_handshake_stress":{"max_time":638.0,"sim_time":95742.614281,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_memory_stress":{"tests":{"dma_memory_stress":{"max_time":155.0,"sim_time":60424.376537000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_generic_stress":{"tests":{"dma_generic_stress":{"max_time":171.0,"sim_time":34009.563892,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_mem_buffer_overflow":{"tests":{"dma_handshake_stress":{"max_time":638.0,"sim_time":95742.614281,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_abort":{"tests":{"dma_abort":{"max_time":5.0,"sim_time":256.701347,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_stress_all":{"tests":{"dma_stress_all":{"max_time":57.0,"sim_time":7465.760668999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"dma_alert_test":{"max_time":1.0,"sim_time":40.216181,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"dma_intr_test":{"max_time":1.0,"sim_time":44.303241,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"dma_tl_errors":{"max_time":2.0,"sim_time":454.26997600000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"dma_tl_errors":{"max_time":2.0,"sim_time":454.26997600000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":14.61341,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":1.0,"sim_time":27.824643000000002,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":6.0,"sim_time":442.701655,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":2.0,"sim_time":386.72186800000003,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":14.61341,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":1.0,"sim_time":27.824643000000002,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":6.0,"sim_time":442.701655,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":2.0,"sim_time":386.72186800000003,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":13,"total":13,"percent":100.0},"V2S":{"testpoints":{"dma_illegal_addr_range":{"tests":{"dma_mem_enabled":{"max_time":14.0,"sim_time":895.083075,"passed":1,"total":1,"percent":100.0},"dma_generic_stress":{"max_time":171.0,"sim_time":34009.563892,"passed":1,"total":1,"percent":100.0},"dma_handshake_stress":{"max_time":638.0,"sim_time":95742.614281,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_config_lock":{"tests":{"dma_config_lock":{"max_time":7.0,"sim_time":322.345478,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_intg_err":{"tests":{"dma_tl_intg_err":{"max_time":3.0,"sim_time":1431.179006,"passed":1,"total":1,"percent":100.0},"dma_sec_cm":{"max_time":1.0,"sim_time":21.758414000000002,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"dma_short_transfer":{"max_time":96.0,"sim_time":8661.37336,"passed":1,"total":1,"percent":100.0},"dma_longer_transfer":{"max_time":4.0,"sim_time":880.128237,"passed":1,"total":1,"percent":100.0},"dma_stress_all_with_rand_reset":{"max_time":6.0,"sim_time":295.257404,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667}},"coverage":{"code":{"block":97.34,"line_statement":96.85,"branch":95.76,"condition_expression":null,"toggle":83.12,"fsm":90.14},"assertion":95.87,"functional":58.98},"cov_report_page":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"dma_stress_all_with_rand_reset","qual_name":"0.dma_stress_all_with_rand_reset.73693474387302907752394194837549199209678972033267228858615695334002123152931","seed":73693474387302907752394194837549199209678972033267228858615695334002123152931,"line":112,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  295257404ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":24,"total":25,"percent":96.0}