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Summary ---\n","\n","\n"]},{"name":"otp_ctrl_parallel_key_req","qual_name":"0.otp_ctrl_parallel_key_req.83857763155066752658056527537158242792225461324315878306217677518121088271831","seed":83857763155066752658056527537158242792225461324315878306217677518121088271831,"line":2894,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest/run.log","log_context":["UVM_INFO @  94282209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_test_access","qual_name":"0.otp_ctrl_test_access.56067766704822307605714158778736970636328493664602409265465870537261051888260","seed":56067766704822307605714158778736970636328493664602409265465870537261051888260,"line":17289,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log","log_context":["UVM_INFO @ 809008363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*":[{"name":"otp_ctrl_macro_errs","qual_name":"0.otp_ctrl_macro_errs.93492601516324059113217900936720963084887764472188173031099217246886976122127","seed":93492601516324059113217900936720963084887764472188173031099217246886976122127,"line":13800,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest/run.log","log_context":["UVM_INFO @ 18616556264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.30037609612581916647585138476431700671234651094895122187749323284567717268900","seed":30037609612581916647585138476431700671234651094895122187749323284567717268900,"line":7700,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 902451755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"otp_ctrl_sec_cm","qual_name":"0.otp_ctrl_sec_cm.101047661826304790545174988159364208290258567695280259090399554805644409281142","seed":101047661826304790545174988159364208290258567695280259090399554805644409281142,"line":2863,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest/run.log","log_context":["UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":20,"total":30,"percent":66.66666666666667}