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Summary ---\n","\n","\n"]},{"name":"otp_ctrl_test_access","qual_name":"0.otp_ctrl_test_access.4155088068198180563578848303550772701518483770826816133616160138284906161979","seed":4155088068198180563578848303550772701518483770826816133616160138284906161979,"line":2526,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log","log_context":["UVM_INFO @ 204788165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*":[{"name":"otp_ctrl_check_fail","qual_name":"0.otp_ctrl_check_fail.21355952311436233672344562481910988911067431439751837753691371638525543784945","seed":21355952311436233672344562481910988911067431439751837753691371638525543784945,"line":4126,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log","log_context":["UVM_INFO @ 883753457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_macro_errs","qual_name":"0.otp_ctrl_macro_errs.69098240604130367105426967619956027044945899312669343680261333009516944022364","seed":69098240604130367105426967619956027044945899312669343680261333009516944022364,"line":12725,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest/run.log","log_context":["UVM_INFO @ 2679310630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.27580075570127106111718545053445922673104934589939997973387103176737953980148","seed":27580075570127106111718545053445922673104934589939997973387103176737953980148,"line":26346,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1318939284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr":[{"name":"otp_ctrl_stress_all","qual_name":"0.otp_ctrl_stress_all.14318977362474921111137556458433383918882909835664170317047098732718968273718","seed":14318977362474921111137556458433383918882909835664170317047098732718968273718,"line":9065,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 279413505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":20,"total":30,"percent":66.66666666666667}