{"block":{"name":"clkmgr","variant":null,"commit":"0e745b4491170b1bf76a14f9c73bea680744e599","commit_short":"0e745b4","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/0e745b4491170b1bf76a14f9c73bea680744e599","revision_info":"GitHub Revision: [`0e745b4`](https://github.com/lowrisc/opentitan/tree/0e745b4491170b1bf76a14f9c73bea680744e599)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-07-06T19:39:26Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":0.98,"sim_time":18.616594,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.74,"sim_time":16.213383,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":2.3,"sim_time":150.657109,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":0.87,"sim_time":25.14839,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.48,"sim_time":72.29186800000001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.87,"sim_time":25.14839,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"passed":2,"total":6,"percent":33.333333333333336},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":0.73,"sim_time":14.426891,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":1.34,"sim_time":85.141808,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":0.98,"sim_time":44.547093999999994,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":0.98,"sim_time":18.616594,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":0.65,"sim_time":4.7590259999999995,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.65,"sim_time":5.932158,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":0.65,"sim_time":4.7590259999999995,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":0.86,"sim_time":15.310606,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":0.97,"sim_time":18.911583,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.79,"sim_time":123.776888,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.79,"sim_time":123.776888,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.74,"sim_time":16.213383,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.87,"sim_time":25.14839,"passed":0,"total":1,"percent":0.0},"clkmgr_same_csr_outstanding":{"max_time":0.94,"sim_time":22.773198,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":4,"percent":50.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":0.74,"sim_time":16.213383,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.87,"sim_time":25.14839,"passed":0,"total":1,"percent":0.0},"clkmgr_same_csr_outstanding":{"max_time":0.94,"sim_time":22.773198,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":4,"percent":50.0}},"passed":8,"total":13,"percent":61.53846153846154},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":84.38,"sim_time":10121.947385,"passed":0,"total":1,"percent":0.0},"clkmgr_tl_intg_err":{"max_time":0.69,"sim_time":9.973072,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.21,"sim_time":59.12275,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.21,"sim_time":59.12275,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.21,"sim_time":59.12275,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.21,"sim_time":59.12275,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":1.23,"sim_time":56.108895,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":0.69,"sim_time":9.973072,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":0.65,"sim_time":4.7590259999999995,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.65,"sim_time":5.932158,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.21,"sim_time":59.12275,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":0.78,"sim_time":20.407387999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":84.38,"sim_time":10121.947385,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.64,"sim_time":4.503614,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":84.38,"sim_time":10121.947385,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":2,"total":8,"percent":25.0},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":0.58,"sim_time":3.0277489999999996,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":2.58,"sim_time":128.12499499999998,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":81.71,"branch":86.53,"condition_expression":79.11,"toggle":91.04,"fsm":0.0},"assertion":90.08,"functional":67.75},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.30569877264083582311728581377248493184776344214747530307269316038818968596629","seed":30569877264083582311728581377248493184776344214747530307269316038818968596629,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_INFO @   4759026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.65571415975750071592325288367678970540018072022821461422036815921435920897279","seed":65571415975750071592325288367678970540018072022821461422036815921435920897279,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_INFO @  15310606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.64563360789385301653899523201861808320662217872944880965464001628056839363842","seed":64563360789385301653899523201861808320662217872944880965464001628056839363842,"line":78,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_INFO @   5932158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.62192473070185835145558096187831744970579144000371488619825210500704088608868","seed":62192473070185835145558096187831744970579144000371488619825210500704088608868,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 128124995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.37420082481441862733519412025357942228470715911774632864239101443697389538943","seed":37420082481441862733519412025357942228470715911774632864239101443697389538943,"line":74,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_INFO @   3027749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.68696616147635395590310138115711188141706348525031544599282506827971515598567","seed":68696616147635395590310138115711188141706348525031544599282506827971515598567,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_INFO @  56108895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_aliasing","qual_name":"0.clkmgr_csr_aliasing.72131823176815635060534539229544509770635228277079970006251230679651943147337","seed":72131823176815635060534539229544509770635228277079970006251230679651943147337,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_INFO @  25148390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.100117736572045625912870948584989740897285729634198192218109675737470441420012","seed":100117736572045625912870948584989740897285729634198192218109675737470441420012,"line":125,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_INFO @ 10121947385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.28205391180395328840934773839796279182014995982159509946635124536717433691928","seed":28205391180395328840934773839796279182014995982159509946635124536717433691928,"line":79,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_INFO @   9973072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"0.clkmgr_csr_rw.85999749009078975020681408642152205880466600594342909843648483541181562138513","seed":85999749009078975020681408642152205880466600594342909843648483541181562138513,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log","log_context":["UVM_INFO @   4503614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.75285906365699006389483026235295335011394432322741709617014496873211055334486","seed":75285906365699006389483026235295335011394432322741709617014496873211055334486,"line":76,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  72291868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.66354618016279768711609838059472425246435888799894762549999168823754230642324","seed":66354618016279768711609838059472425246435888799894762549999168823754230642324,"line":75,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @ 150657109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":10,"total":22,"percent":45.45454545454545}