{"block":{"name":"chip","variant":null,"commit":"197a51961fe72812610e178dde182d889cbe5cbc","commit_short":"197a519","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/197a51961fe72812610e178dde182d889cbe5cbc","revision_info":"GitHub Revision: [`197a519`](https://github.com/lowrisc/opentitan/tree/197a51961fe72812610e178dde182d889cbe5cbc)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-07-08T19:40:29Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":13.10875475499779,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":13.10875475499779,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_uart_rand_baudrate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":13.177206323016435,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":18.12998002395034,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":312.21,"sim_time":295.126289,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":312.21,"sim_time":295.126289,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":312.21,"sim_time":295.126289,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_example_tests":{"tests":{"chip_sw_example_rom":{"max_time":35.39,"sim_time":10.340001,"passed":0,"total":1,"percent":0.0},"chip_sw_example_manufacturer":{"max_time":8.882490599062294,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_example_concurrency":{"max_time":199.09,"sim_time":168.708,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_smoketest_signed":{"max_time":8.307159536052495,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":4,"percent":25.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":9.37,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":9.55,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":9.55,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":9.16,"sim_time":13.144413,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":3,"total":11,"percent":27.272727272727273},"V2":{"testpoints":{"chip_sw_spi_device_flash_mode":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":71.57661233888939,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":2052.31,"sim_time":3828.549377,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":300.12,"sim_time":267.93,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":9.957023590803146,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":9.450097837019712,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":8.887325906660408,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":10.920810034964234,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":3.06,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":3.06,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":12.242553215008229,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":11.307220426853746,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":9.447139107156545,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":9.447139107156545,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":116.67,"sim_time":132.035,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":103.84,"sim_time":131.238,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":300.55,"sim_time":309.947,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":8.698865852784365,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":8.209906792268157,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":90.29,"sim_time":120.728,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":259.04,"sim_time":266.867,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":405.08,"sim_time":483.292,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":405.08,"sim_time":483.292,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":409.47,"sim_time":386.626,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":255.10000000000002,"sim_time":182.403,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":255.10000000000002,"sim_time":182.403,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":351.55,"sim_time":2310.131,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":180.25,"sim_time":164.269,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":305.89,"sim_time":245.086,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_idle":{"max_time":196.4,"sim_time":165.844,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":205.01,"sim_time":178.105,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_idle":{"max_time":191.36,"sim_time":164.058,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":208.42,"sim_time":185.328,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":216.78,"sim_time":185.28,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":199.41,"sim_time":185.312,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":198.95,"sim_time":185.184,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":4,"percent":0.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":40.51,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"chip_sw_aes_enc_jitter_en":{"max_time":39.68,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"chip_sw_hmac_enc_jitter_en":{"max_time":42.72,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":40.98,"sim_time":10.100001,"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":42.1,"sim_time":10.180001,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":11.706422205083072,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_jitter":{"max_time":199.33,"sim_time":161.281,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":7,"percent":14.285714285714286},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":405.94,"sim_time":1962.489582,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":41.9,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":39.43,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":42.11,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq":{"max_time":43.41,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":42.94,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":42.39,"sim_time":10.200001,"passed":0,"total":1,"percent":0.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":41.22,"sim_time":10.240001,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":8,"percent":12.5},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":10.247156281024218,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":8.843147430103272,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":10.095140076242387,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":119.42,"sim_time":118.488,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_sleep_all_reset_reqs":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":255.10000000000002,"sim_time":182.403,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":10.478889903053641,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_aon_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":119.42,"sim_time":118.488,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":12.259432589169592,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":16.999785827938467,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":13.290279492270201,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":12.339108670130372,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":14.903479599859565,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":300.55,"sim_time":309.947,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":409.41,"sim_time":412.016,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":343.16,"sim_time":305.324,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":373.81,"sim_time":331.169,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":188.78,"sim_time":163.696,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":10.949361309874803,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":38.097261286806315,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":25.39890731777996,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":373.81,"sim_time":331.169,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":351.39,"sim_time":378.754,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":65.11943824728951,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":87.78136213496327,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":68.43137578899041,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":85.51599345123395,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":89.8734207036905,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":38.097261286806315,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_otp_hw_cfg":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg":{"max_time":9.510074171237648,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_dpe_key_derivation_prod":{"max_time":355.15,"sim_time":304.833,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":15.70157374208793,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":24.48263493971899,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":17.735346911940724,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":21.971052945125848,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":329.45,"sim_time":304.762,"passed":0,"total":1,"percent":0.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":185.19,"sim_time":157.256,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_execution_main":{"max_time":9.861438241321594,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_prim_tl_access":{"max_time":83.15,"sim_time":118.024,"passed":0,"total":1,"percent":0.0},"chip_rv_dm_lc_disabled":{"max_time":90.29,"sim_time":120.728,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":212.35,"sim_time":173.08,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":39.68,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_aes_gcm":{"tests":{"chip_sw_aes_enc":{"max_time":212.35,"sim_time":173.08,"passed":1,"total":1,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":39.68,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":196.75,"sim_time":164.418,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":196.4,"sim_time":165.844,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":195.18,"sim_time":173.839,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":42.72,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":205.01,"sim_time":178.105,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":209.4,"sim_time":167.325,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":248.25,"sim_time":188.957,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":42.1,"sim_time":10.180001,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":329.45,"sim_time":304.762,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":16.270536246243864,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":258.49,"sim_time":202.733,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":191.36,"sim_time":164.058,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":1643.12,"sim_time":2224.012,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":1643.12,"sim_time":2224.012,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":9.089710329193622,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":209.67,"sim_time":175.98,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":1127.87,"sim_time":704.76,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":329.45,"sim_time":304.762,"passed":0,"total":1,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":40.98,"sim_time":10.100001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":3015.47,"sim_time":1493.342,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":40.51,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":305.89,"sim_time":245.086,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":305.89,"sim_time":245.086,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":305.89,"sim_time":245.086,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":440.5,"sim_time":280.795,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":185.19,"sim_time":157.256,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":185.19,"sim_time":157.256,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":457.49,"sim_time":350.146234,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":11.706422205083072,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":9.861438241321594,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0},"chip_sw_data_integrity_escalation":{"max_time":9.447139107156545,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":440.5,"sim_time":280.795,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":329.45,"sim_time":304.762,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":457.49,"sim_time":350.146234,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":205.44,"sim_time":179.794038,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":4,"percent":75.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":440.5,"sim_time":280.795,"passed":1,"total":1,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":329.45,"sim_time":304.762,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":457.49,"sim_time":350.146234,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":205.44,"sim_time":179.794038,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":4,"percent":75.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":8.786993492860347,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_hw_cfg":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg":{"max_time":9.510074171237648,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":15.70157374208793,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":24.48263493971899,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":17.735346911940724,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":21.971052945125848,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":9.757377459201962,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_prim_tl_access":{"max_time":83.15,"sim_time":118.024,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":83.15,"sim_time":118.024,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_nvm_cnt":{"tests":{"chip_sw_otp_ctrl_nvm_cnt":{"max_time":28.227934760041535,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_sw_parts":{"tests":{"chip_sw_otp_ctrl_sw_parts":{"max_time":9.643775513861328,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":10.247156281024218,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":40.51,"sim_time":10.320001,"passed":0,"total":1,"percent":0.0},"chip_sw_aes_enc_jitter_en":{"max_time":39.68,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"chip_sw_hmac_enc_jitter_en":{"max_time":42.72,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":40.98,"sim_time":10.100001,"passed":0,"total":1,"percent":0.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":42.1,"sim_time":10.180001,"passed":0,"total":1,"percent":0.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":11.706422205083072,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_clkmgr_jitter":{"max_time":199.33,"sim_time":161.281,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":7,"percent":14.285714285714286},"chip_sw_soc_proxy_external_reset_requests":{"tests":{"chip_sw_soc_proxy_smoketest":{"max_time":185.89,"sim_time":156.16,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_soc_proxy_external_irqs":{"tests":{"chip_sw_soc_proxy_smoketest":{"max_time":185.89,"sim_time":156.16,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_soc_proxy_external_wakeup_requests":{"tests":{"chip_sw_soc_proxy_external_wakeup":{"max_time":197.02,"sim_time":157.829,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_soc_proxy_gpios":{"tests":{"chip_sw_soc_proxy_gpios":{"max_time":193.75,"sim_time":172.38589499999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":397.95,"sim_time":269.308,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":216.5,"sim_time":178.627,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":238.19,"sim_time":179.942,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":205.44,"sim_time":179.794038,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":409.41,"sim_time":412.016,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":409.41,"sim_time":412.016,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_smoketest":{"tests":{"chip_sw_aes_smoketest":{"max_time":214.63,"sim_time":173.109,"passed":1,"total":1,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":230.18,"sim_time":182.276,"passed":1,"total":1,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":198.39,"sim_time":162.074,"passed":1,"total":1,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":210.58,"sim_time":164.185,"passed":1,"total":1,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":198.17,"sim_time":184.49582999999998,"passed":1,"total":1,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":247.65000000000003,"sim_time":194.781,"passed":1,"total":1,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":226.78,"sim_time":185.464,"passed":1,"total":1,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":336.64,"sim_time":239.41,"passed":1,"total":1,"percent":100.0},"chip_sw_otp_ctrl_smoketest":{"max_time":187.14,"sim_time":165.837,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":204.07,"sim_time":163.956,"passed":1,"total":1,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":275.33,"sim_time":266.838,"passed":1,"total":1,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":184.18,"sim_time":160.917,"passed":1,"total":1,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":194.95,"sim_time":164.456,"passed":1,"total":1,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":205.75,"sim_time":175.139,"passed":1,"total":1,"percent":100.0}},"passed":14,"total":14,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":8.75446974299848,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_signed":{"tests":{"chip_sw_uart_smoketest_signed":{"max_time":8.307159536052495,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":71.57661233888939,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_secure_boot":{"tests":{"base_rom_e2e_smoke":{"max_time":8.238878542091697,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":207.67,"sim_time":171.672,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":150.73,"sim_time":172.456,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":168.79,"sim_time":174.696,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":161.83,"sim_time":173.512,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":4,"percent":0.0},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":9.645794354844838,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_rv_dm_lc_disabled":{"max_time":90.29,"sim_time":120.728,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":92.15337942587212,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":72.03751330403611,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":9.026029049884528,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_rma":{"max_time":86.58510230667889,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":9.645794354844838,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":259.85,"sim_time":362.824,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":428.94,"sim_time":589.88,"passed":0,"total":1,"percent":0.0},"rom_volatile_raw_unlock":{"max_time":14.50412888173014,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":14.470537915825844,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":64.30000395607203,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":78.69146588118747,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":128.47,"sim_time":118.019,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":128.47,"sim_time":118.019,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":9.55,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_same_csr_outstanding":{"max_time":9.52,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":9.55,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_same_csr_outstanding":{"max_time":9.52,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":83.1,"sim_time":177.6671,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":8.93,"sim_time":10.972513000000001,"passed":1,"total":1,"percent":100.0},"xbar_smoke_large_delays":{"max_time":243.48,"sim_time":2328.578678,"passed":1,"total":1,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":364.46,"sim_time":2193.43061,"passed":1,"total":1,"percent":100.0},"xbar_random_zero_delays":{"max_time":98.68,"sim_time":74.695535,"passed":1,"total":1,"percent":100.0},"xbar_random_large_delays":{"max_time":879.95,"sim_time":8299.329456,"passed":1,"total":1,"percent":100.0},"xbar_random_slow_rsp":{"max_time":410.14,"sim_time":2572.75979,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":86.84,"sim_time":135.668799,"passed":1,"total":1,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":16.05,"sim_time":31.45682,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":34.99,"sim_time":38.051536999999996,"passed":1,"total":1,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":16.05,"sim_time":31.45682,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":50.47,"sim_time":45.404576,"passed":1,"total":1,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":2812.51,"sim_time":19214.477796,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":11.32,"sim_time":11.818929,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":579.68,"sim_time":430.736896,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_error":{"max_time":890.69,"sim_time":2263.3831099999998,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":1066.2,"sim_time":614.4750779999999,"passed":1,"total":1,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":106.14,"sim_time":64.71163,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":8.390532263088971,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":10.983341854065657,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":19.280336361844093,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":46.83747345302254,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":9.524026382248849,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":11.297888340894133,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":8.61752473283559,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":9.566904456820339,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":51.80014994274825,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":9.910882492084056,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":8.996297804173082,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":8.44580586720258,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":11.592128943186253,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":54.106643937993795,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":13.964428968727589,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":19.55583135318011,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":11.55219697020948,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":12.272847331129014,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":63.31782275112346,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":13.936182901263237,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":21.306627073790878,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":23.907063017133623,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":19.603217614348978,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":35.67451048921794,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":18.818094059359282,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":12.77426935499534,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":15.289311132859439,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":14.472699047066271,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":32.4950944702141,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":17.562969878315926,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":12.433991963975132,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":20.836463631130755,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":14.136522686108947,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":56.731123563833535,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":8.5575313558802,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":17.942496755626053,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":22.121191176585853,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":23.516014283988625,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":5,"percent":0.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":12.562973785214126,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":9.218163671903312,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":31.29399668611586,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":10.528583738021553,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":62,"total":199,"percent":31.155778894472363},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":240.62999999999997,"sim_time":187.939142,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":172.32,"sim_time":136.2925,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":14.307245809119195,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":12.363396359141916,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":14.625713686924428,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":11.5917257219553,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":1060.82,"sim_time":943.774,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":14.546960341744125,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":229.98,"sim_time":177.04,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":31.80879989732057,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":80.54195043211803,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":14.307245809119195,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":12.363396359141916,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":14.625713686924428,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":49.98242258699611,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":58.157421107869595,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":52.179567319806665,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":42.50923535274342,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":13,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":43.76,"sim_time":10.300001,"passed":0,"total":1,"percent":0.0},"chip_sw_aes_gcm":{"max_time":267.67,"sim_time":203.559,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_kat_test":{"max_time":182.78,"sim_time":163.559,"passed":1,"total":1,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":170.74,"sim_time":161.174,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_0":{"max_time":415.95,"sim_time":327.709,"passed":1,"total":1,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":400.14,"sim_time":300.541,"passed":1,"total":1,"percent":100.0},"chip_sw_dma_inline_hashing":{"max_time":232.48,"sim_time":210.488,"passed":1,"total":1,"percent":100.0},"chip_sw_dma_abort":{"max_time":265.14,"sim_time":211.676,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn":{"max_time":19.874898850917816,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_test_unlocked0_sw":{"max_time":16.897638078778982,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_dev_otbn":{"max_time":12.33921039616689,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_dev_sw":{"max_time":11.386748749762774,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_otbn":{"max_time":11.090918397996575,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_sw":{"max_time":10.847826421260834,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_end_otbn":{"max_time":8.757020291872323,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_prod_end_sw":{"max_time":13.407697677146643,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_rma_otbn":{"max_time":8.590613062959164,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_mod_exp_rma_sw":{"max_time":9.763879808131605,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_entropy_src_smoketest":{"max_time":252.71999999999997,"sim_time":194.778,"passed":1,"total":1,"percent":100.0},"chip_sw_mbx_smoketest":{"max_time":496.41,"sim_time":405.995636,"passed":1,"total":1,"percent":100.0}},"passed":8,"total":20,"percent":40.0}},"passed":8,"total":20,"percent":40.0}},"coverage":{"code":{"block":null,"line_statement":67.3,"branch":75.16,"condition_expression":66.61,"toggle":56.72,"fsm":57.14},"assertion":76.58,"functional":64.67},"cov_report_page":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode":[{"name":"chip_csr_bit_bash","qual_name":"0.chip_csr_bit_bash.51227179956695636700158374465981545376671108892332555996949414931932967189141","seed":51227179956695636700158374465981545376671108892332555996949414931932967189141,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_csr_aliasing","qual_name":"0.chip_csr_aliasing.89106958100326345749209133236142815798793212712228300385763529033299309610105","seed":89106958100326345749209133236142815798793212712228300385763529033299309610105,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"0.chip_same_csr_outstanding.88060988273309483464553342038249613655000220629226364922958031295831303971052","seed":88060988273309483464553342038249613655000220629226364922958031295831303971052,"line":136,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode":[{"name":"chip_sw_example_rom","qual_name":"0.chip_sw_example_rom.18977473664251973211162953153906566925667532696364286672884711248670862236767","seed":18977473664251973211162953153906566925667532696364286672884711248670862236767,"line":289,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_example_manufacturer","qual_name":"0.chip_sw_example_manufacturer.98637261371059091597684329701923228667593866466525833568751412213909474481263","seed":98637261371059091597684329701923228667593866466525833568751412213909474481263,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.297s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_data_integrity_escalation","qual_name":"0.chip_sw_data_integrity_escalation.47028576600822992133054602481413879749301053551943422411215905583821553060568","seed":47028576600822992133054602481413879749301053551943422411215905583821553060568,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.342s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.2462275192669078171254946376856381278192194516587541249958476552776054943925","seed":2462275192669078171254946376856381278192194516587541249958476552776054943925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_wake_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.215s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.21023328504770766824382943936477166398374300231982591813876409389016543810339","seed":21023328504770766824382943936477166398374300231982591813876409389016543810339,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:sleep_pin_retention_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.285s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx","qual_name":"0.chip_sw_uart_tx_rx.56888976722668886620650726195610404875315549417963743998376169572591503611490","seed":56888976722668886620650726195610404875315549417963743998376169572591503611490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.416s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.94876556947421984148894734125720444718897461686774981218613902319666141636207","seed":94876556947421984148894734125720444718897461686774981218613902319666141636207,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.590s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_inject_scramble_seed","qual_name":"0.chip_sw_inject_scramble_seed.48864499252306142144842310385907852813065369763561891760700606866411107339574","seed":48864499252306142144842310385907852813065369763561891760700606866411107339574,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:inject_scramble_seed_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:inject_scramble_seed_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.705s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.19653964642556486914801999472976529052280488719154540901728317290130758948197","seed":19653964642556486914801999472976529052280488719154540901728317290130758948197,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:exit_test_unlocked_bootstrap_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.641s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_rand_baudrate","qual_name":"0.chip_sw_uart_rand_baudrate.62840794049768227988098887385153481145836963897094935063625160171090490654483","seed":62840794049768227988098887385153481145836963897094935063625160171090490654483,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.749s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_tx_rx_alt_clk_freq","qual_name":"0.chip_sw_uart_tx_rx_alt_clk_freq.48958888097033135295042696587308108189199970609516426285783852078022145709783","seed":48958888097033135295042696587308108189199970609516426285783852078022145709783,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:uart_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.683s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_host_tx_rx","qual_name":"0.chip_sw_i2c_host_tx_rx.49132918166379386678966348349911827047875101082330459443454800459162815136785","seed":49132918166379386678966348349911827047875101082330459443454800459162815136785,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.262s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_i2c_device_tx_rx","qual_name":"0.chip_sw_i2c_device_tx_rx.103680482036779051208217485634764285157691038692041976135801838368415344357318","seed":103680482036779051208217485634764285157691038692041976135801838368415344357318,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_i2c_device_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:i2c_device_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.375s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_device_tpm","qual_name":"0.chip_sw_spi_device_tpm.57006658843488708894738055409549286429594024443726337782711139057571449379133","seed":57006658843488708894738055409549286429594024443726337782711139057571449379133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_tpm/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:spi_device_tpm_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.280s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_spi_host_tx_rx","qual_name":"0.chip_sw_spi_host_tx_rx.33755160210672982205288490761654608463564364758092771879932660324803392807701","seed":33755160210672982205288490761654608463564364758092771879932660324803392807701,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:spi_host_tx_rx_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.265s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_otp_hw_cfg","qual_name":"0.chip_sw_lc_ctrl_otp_hw_cfg.97929442343264109918051187515949496421415179339714572104570426868151910392452","seed":97929442343264109918051187515949496421415179339714572104570426868151910392452,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_otp_hw_cfg/latest/run.log","log_context":["\n","Waiting for it to complete...\n","Another command (pid=1165834) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: no such target '//sw/device/tests:lc_ctrl_otp_hw_cfg_test_sim_dv': target 'lc_ctrl_otp_hw_cfg_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean lc_ctrl_otp_hw_cfg0_test_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_test_unlocked0","qual_name":"0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.100488629146775446569030517492790470331199579604412843140986530584934582249112","seed":100488629146775446569030517492790470331199579604412843140986530584934582249112,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.649s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_dev","qual_name":"0.chip_sw_otp_ctrl_lc_signals_dev.44350683877588037837534732568455845640014558993256298003076282550282339794055","seed":44350683877588037837534732568455845640014558993256298003076282550282339794055,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.692s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_prod","qual_name":"0.chip_sw_otp_ctrl_lc_signals_prod.91879823742480724387717248218872411622846973012765486403496902655681602104196","seed":91879823742480724387717248218872411622846973012765486403496902655681602104196,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.202s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.37283317875709104580206855686574272576573458298911200371164569311060917705696","seed":37283317875709104580206855686574272576573458298911200371164569311060917705696,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_lc_signals_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.811s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_vendor_test_csr_access","qual_name":"0.chip_sw_otp_ctrl_vendor_test_csr_access.85120105314664786600424465541436989560930062246827156104149742304691974573286","seed":85120105314664786600424465541436989560930062246827156104149742304691974573286,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:otp_ctrl_vendor_test_csr_access_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 3.214s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_nvm_cnt","qual_name":"0.chip_sw_otp_ctrl_nvm_cnt.26428518796292614494460712798448144613374012945038394583445053116667941081898","seed":26428518796292614494460712798448144613374012945038394583445053116667941081898,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_nvm_cnt/latest/run.log","log_context":["Another command (pid=351385) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=369224) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=365144) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_nvm_cnt_test_sim_dv': target 'otp_ctrl_nvm_cnt_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_otp_ctrl_sw_parts","qual_name":"0.chip_sw_otp_ctrl_sw_parts.17536438038638076918046435015231060695039719616426450600340761558444262337197","seed":17536438038638076918046435015231060695039719616426450600340761558444262337197,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_sw_parts/latest/run.log","log_context":["Another command (pid=454169) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=460575) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=463486) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:otp_ctrl_sw_parts_test_sim_dv': target 'otp_ctrl_sw_parts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.3794421441792268327560028581195631751292478902483492110946198992575686178224","seed":3794421441792268327560028581195631751292478902483492110946198992575686178224,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["Analyzing: 2 targets (0 packages loaded, 0 targets configured)\n","\n","Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_transition_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.231s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.6847258232344478390842803646981097135654825027095318064193698140155865841796","seed":6847258232344478390842803646981097135654825027095318064193698140155865841796,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.520s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.90388379923994910942700373214645541918984022390084738959756531223976914695902","seed":90388379923994910942700373214645541918984022390084738959756531223976914695902,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.572s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_prodend","qual_name":"0.chip_sw_lc_walkthrough_prodend.51523284838029565713819593594174790857720863211924857226344514184146990649396","seed":51523284838029565713819593594174790857720863211924857226344514184146990649396,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.254s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.33739621487288761220411085786508782490015977401916361088129055561721173574053","seed":33739621487288761220411085786508782490015977401916361088129055561721173574053,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 5.757s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.83232652519196804700393726781912148581561058560547493986006280983659081485972","seed":83232652519196804700393726781912148581561058560547493986006280983659081485972,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.726s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_main_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_main_power_glitch_reset.6195068926815374671137747457461955304466880750780410812535416944510241005913","seed":6195068926815374671137747457461955304466880750780410812535416944510241005913,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.879s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.79978157905262057445203467495909065446031418500778025945491613336512548019867","seed":79978157905262057445203467495909065446031418500778025945491613336512548019867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.637s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.112488785794446005507385252142406277976154244398461681630932851098277075690542","seed":112488785794446005507385252142406277976154244398461681630932851098277075690542,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.684s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1707596924764853300984018324491039487369506734425531271834686016729695850817","seed":1707596924764853300984018324491039487369506734425531271834686016729695850817,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:pwrmgr_random_sleep_power_glitch_reset_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.248s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_disabled","qual_name":"0.chip_sw_pwrmgr_sleep_disabled.95331612491001764546818449581836956031855888797717567900383771673382703599884","seed":95331612491001764546818449581836956031855888797717567900383771673382703599884,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_disabled/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_sleep_disabled_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.118s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_wdog_reset","qual_name":"0.chip_sw_pwrmgr_wdog_reset.16635928514002305981740448215682077975110106782625787204739619914494326331047","seed":16635928514002305981740448215682077975110106782625787204739619914494326331047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_wdog_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv' failed; build aborted: Target //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:pwrmgr_wdog_reset_reqs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.905s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.60560039948364364767849022145001106365151490735876931344281722738971367215665","seed":60560039948364364767849022145001106365151490735876931344281722738971367215665,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["Another command (pid=694647) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:alert_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - sw/device/tests/autogen/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_escalation","qual_name":"0.chip_sw_alert_handler_escalation.94521346054102769771879347062326484079308847870692992436291885928680799488941","seed":94521346054102769771879347062326484079308847870692992436291885928680799488941,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_escalation/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 26.161s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.91837329289346236476380180978719122547471201585541394923440943077776837673008","seed":91837329289346236476380180978719122547471201585541394923440943077776837673008,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_reverse_ping_in_deep_sleep_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 2.947s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.80652394248959125116729289824506198825886305705718983530986239040777847437711","seed":80652394248959125116729289824506198825886305705718983530986239040777847437711,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["Another command (pid=351385) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=369224) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=365144) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:alert_handler_lpg_sleep_mode_alerts_test_sim_dv': target 'alert_handler_lpg_sleep_mode_alerts_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.87235117109843009377094643522213418963175844245177167129121334410388250387039","seed":87235117109843009377094643522213418963175844245177167129121334410388250387039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_sleep_mode_pings_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.130s, Critical Path: 0.00s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_clkoff","qual_name":"0.chip_sw_alert_handler_lpg_clkoff.13359146731325167482471689806977828197980652265984265209453346612560985643425","seed":13359146731325167482471689806977828197980652265984265209453346612560985643425,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_clkoff/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_clkoff_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 1.313s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_lpg_reset_toggle","qual_name":"0.chip_sw_alert_handler_lpg_reset_toggle.107763690993462631092762861321718967973937705502476461575741413797024291959877","seed":107763690993462631092762861321718967973937705502476461575741413797024291959877,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_lpg_reset_toggle/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 9.731s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.97091403793248590220514119429558797666607145208430891425787956263967205843515","seed":97091403793248590220514119429558797666607145208430891425787956263967205843515,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["ERROR: Analysis of target '//sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:alert_handler_entropy_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 6.224s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","FAILED: \n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.31913078913619818056288397008467726135979258882715477601509739416159451045303","seed":31913078913619818056288397008467726135979258882715477601509739416159451045303,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.324s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_kmac_app_rom","qual_name":"0.chip_sw_kmac_app_rom.61616736238763564541917391547631631320179584005099394759483188016501537012965","seed":61616736238763564541917391547631631320179584005099394759483188016501537012965,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log","log_context":["INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery labels(data, //sw/device/tests:kmac_app_rom_test_sim_dv) union labels(srcs, //sw/device/tests:kmac_app_rom_test_sim_dv) --ui_event_filters=-info --noshow_progress --//hw/top=darjeeling --//hw/top=darjeeling --output=starlark\n","---- STDOUT ----\n","\n","---- STDERR ----\n","Another command (pid=1142730) is running. Waiting for it to complete on the server (server_pid=200843)...\n","ERROR: Error doing post analysis query: Evaluation of subquery \"labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)\" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en.89352852487012236359515089254995305511664172046147403075519666261914204692766","seed":89352852487012236359515089254995305511664172046147403075519666261914204692766,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1354132) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: no such target '//sw/device/tests/sim_dv:sram_ctrl_scrambled_access_test_sim_dv': target 'sram_ctrl_scrambled_access_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_sram_ctrl_execution_main","qual_name":"0.chip_sw_sram_ctrl_execution_main.60517644327750604277686296326849684697784363354673071772435675832136002111585","seed":60517644327750604277686296326849684697784363354673071772435675832136002111585,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:sram_ctrl_execution_main_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.294s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.59683089965303753289540039193443580663089102112919187029637575215570748571305","seed":59683089965303753289540039193443580663089102112919187029637575215570748571305,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_coremark/latest/run.log","log_context":["Another command (pid=351385) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//third_party/coremark/top_darjeeling:coremark_test_sim_dv': no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: no such package 'third_party/coremark/top_darjeeling': BUILD file not found in any of the following directories. Add a BUILD file to a directory to mark it as a package.\n"," - third_party/coremark/top_darjeeling\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.22277444546020448677458640561384899317218604491878386636018267779147734444637","seed":22277444546020448677458640561384899317218604491878386636018267779147734444637,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_reset_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_reset_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_reset_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.272s, Critical Path: 0.01s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.54777066935205837324302263519200888051017110207796985234417815085279964834929","seed":54777066935205837324302263519200888051017110207796985234417815085279964834929,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:clkmgr_sleep_frequency_test_sim_dv' failed; build aborted: Target //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:clkmgr_sleep_frequency_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.269s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_ast_clk_outputs","qual_name":"0.chip_sw_ast_clk_outputs.3356043765057466309737924447940781797875336535171981856927492943961289293469","seed":3356043765057466309737924447940781797875336535171981856927492943961289293469,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_ast_clk_outputs/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:ast_clk_outs_test_sim_dv' failed; build aborted: Target //sw/device/tests:ast_clk_outs_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:ast_clk_outs_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.466s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_lc_ctrl_program_error","qual_name":"0.chip_sw_lc_ctrl_program_error.3464292921138831306678061274185705885720010871547605582822690747669328075210","seed":3464292921138831306678061274185705885720010871547605582822690747669328075210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests/sim_dv:lc_ctrl_program_error_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.238s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.68563230129932910019100940564925426628402595550701526270608284683771859373261","seed":68563230129932910019100940564925426628402595550701526270608284683771859373261,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted_sim_dv': target 'rv_dm_ndm_reset_req_when_cpu_halted_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_ndm_reset_req_when_cpu_halted_dev_sim_dv, or rv_dm_ndm_reset_req_when_cpu_halted_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.43203150765738569831037583801616041036313125444811840859789903182234182459654","seed":43203150765738569831037583801616041036313125444811840859789903182234182459654,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: no such target '//sw/device/tests:rv_dm_access_after_wakeup_sim_dv': target 'rv_dm_access_after_wakeup_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD (did you mean rv_dm_access_after_wakeup_dev_sim_dv, or rv_dm_access_after_wakeup_rma_sim_dv?)\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"0.chip_sw_rv_dm_access_after_escalation_reset.11972189417306035185364506259131049352330586084180787760593607176476064648480","seed":11972189417306035185364506259131049352330586084180787760593607176476064648480,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:alert_handler_escalation_test_sim_dv' failed; build aborted: Target //sw/device/tests:alert_handler_escalation_test_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:alert_handler_escalation_test_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.585s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_power_virus","qual_name":"0.chip_sw_power_virus.83028164145008712460299254123575651303017182376177260182845992989686486933672","seed":83028164145008712460299254123575651303017182376177260182845992989686486933672,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/tests:power_virus_systemtest_sim_dv' failed; build aborted: Target //sw/device/tests:power_virus_systemtest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/tests:power_virus_systemtest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 4.798s, Critical Path: 0.02s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"base_rom_e2e_smoke","qual_name":"0.base_rom_e2e_smoke.15846070561251214893247537210364395274850221420597301030754055753881651279450","seed":15846070561251214893247537210364395274850221420597301030754055753881651279450,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.base_rom_e2e_smoke/latest/run.log","log_context":["    _deploy_software_collateral(args)\n","    ~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^^^^\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 324, in _deploy_software_collateral\n","    image_string = ImageString(image)\n","  File \"<string>\", line 4, in __init__\n","  File \"/nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py\", line 256, in __post_init__\n","    assert flag in KNOWN_FLAGS, f\"Unknown flag '{flag}' used in sw_image '{self.raw}'\"\n","           ^^^^^^^^^^^^^^^^^^^\n","AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_smoke","qual_name":"0.rom_e2e_smoke.93895275110999499246717001113899172809171844588558684178431157425396304179647","seed":93895275110999499246717001113899172809171844588558684178431157425396304179647,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.76781499571633322119772180791738675859931414365488618203763790429577323885232","seed":76781499571633322119772180791738675859931414365488618203763790429577323885232,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["Another command (pid=528745) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=554452) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=560243) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.53694452089920680124908730568267848041627782911899469601205248470814926652592","seed":53694452089920680124908730568267848041627782911899469601205248470814926652592,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["Another command (pid=535662) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=534228) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=533811) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.54265064188369656437466060544848136772467644473508349970774029733570407351110","seed":54265064188369656437466060544848136772467644473508349970774029733570407351110,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=330997) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=283769) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=313436) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.51363952682980377561960096082856709045625232010263000812119568944383592667936","seed":51363952682980377561960096082856709045625232010263000812119568944383592667936,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["Another command (pid=482439) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=488849) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=503467) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.12154191862211433191099402831481997811942407813951308038412212737689718818163","seed":12154191862211433191099402831481997811942407813951308038412212737689718818163,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["Another command (pid=508852) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=510117) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=505793) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.87403674793736373222600716023590866358047656678113710994021338140472403353214","seed":87403674793736373222600716023590866358047656678113710994021338140472403353214,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=506247) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.91130907104675536707689424243751263155376394132953792042502296820212603136851","seed":91130907104675536707689424243751263155376394132953792042502296820212603136851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["Another command (pid=502684) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=510117) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=505793) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.67182005300298451646498816267244800810149268892807185847894155791110514594316","seed":67182005300298451646498816267244800810149268892807185847894155791110514594316,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=301350) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=313436) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=289374) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.56202234997591080092528226333893937921937938165309563842465545087182175401319","seed":56202234997591080092528226333893937921937938165309563842465545087182175401319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["Another command (pid=483917) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=466930) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=484336) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.85674761984062335972557367114479731545149137996442393564207809477967837649223","seed":85674761984062335972557367114479731545149137996442393564207809477967837649223,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=483917) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=466930) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.104247965788094685454327368896278545728513652172128078535510877024625699773469","seed":104247965788094685454327368896278545728513652172128078535510877024625699773469,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=466930) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.38658931243923249299236475334954246952890059748621922031277906128916242152327","seed":38658931243923249299236475334954246952890059748621922031277906128916242152327,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["Another command (pid=484926) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=471869) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=474520) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.11496518925186443159347041139770728142940522843156545973694569720318812134124","seed":11496518925186443159347041139770728142940522843156545973694569720318812134124,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=280311) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.27121464141959320055857727253000306735535446145687246755691148721349464976173","seed":27121464141959320055857727253000306735535446145687246755691148721349464976173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=368158) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.99448815623394714492380627356088044143237272600116329346761496572121748154113","seed":99448815623394714492380627356088044143237272600116329346761496572121748154113,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["Another command (pid=469139) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=496904) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=497325) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.109302886209929971178086878071288489484239897069286986793090446221591533920458","seed":109302886209929971178086878071288489484239897069286986793090446221591533920458,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=469853) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.115556584478162852766716488769338798730197619860485012692698299392839357686479","seed":115556584478162852766716488769338798730197619860485012692698299392839357686479,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=471869) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=474520) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_sim_dv': target 'empty_test_slot_b_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.17073176622020117347784766208273907087558417132626992561316568740775836054913","seed":17073176622020117347784766208273907087558417132626992561316568740775836054913,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=310552) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.69091103634141292911124848433200067405102364839823079214674972754464015841925","seed":69091103634141292911124848433200067405102364839823079214674972754464015841925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=549407) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=552786) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.49642316093751547853961931325667257468415589158346878820040089890212252672594","seed":49642316093751547853961931325667257468415589158346878820040089890212252672594,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["Another command (pid=568843) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=565564) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=559716) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.92790815666039011069070810888748259246028583977576392072728325734502712783061","seed":92790815666039011069070810888748259246028583977576392072728325734502712783061,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["Another command (pid=566525) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=571208) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=552127) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.29819991510542295503873124827084193909768432120989965691539378487806090937717","seed":29819991510542295503873124827084193909768432120989965691539378487806090937717,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=575888) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.77137059758372173678906918779982355235077707183522086872277927675941014837636","seed":77137059758372173678906918779982355235077707183522086872277927675941014837636,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=330304) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.101412089679402655358229894671095977137900749736661183361573857152857912444741","seed":101412089679402655358229894671095977137900749736661183361573857152857912444741,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["Another command (pid=551206) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=524804) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=584832) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.42694546064835505415554924256884654286028986433094424032483635593675281022979","seed":42694546064835505415554924256884654286028986433094424032483635593675281022979,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["Another command (pid=561389) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=556285) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=568843) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.23588365643381919843362167804084149527095254296629108342047308680260572480751","seed":23588365643381919843362167804084149527095254296629108342047308680260572480751,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["Another command (pid=558897) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=566525) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=571208) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.5006767070396616772912223598281540140938199788412308220809978129238624424558","seed":5006767070396616772912223598281540140938199788412308220809978129238624424558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["Another command (pid=571208) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=552127) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=551206) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.68449252513834268472265672080217247679596321692565730674045240167150473942558","seed":68449252513834268472265672080217247679596321692565730674045240167150473942558,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=296491) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_test_unlocked0': target 'otp_img_sigverify_always_test_unlocked0' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.106074780641826926057618322190769661231908762487589601033165360724512900900210","seed":106074780641826926057618322190769661231908762487589601033165360724512900900210,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["Another command (pid=588119) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=589268) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=568373) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_dev': target 'otp_img_sigverify_always_dev' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.14156285369790812213956373226002026837137188171086848641652449844797582254389","seed":14156285369790812213956373226002026837137188171086848641652449844797582254389,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=569954) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=566525) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod': target 'otp_img_sigverify_always_prod' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.114006972768070745689169941537672783511558094441993283599713298597544575423459","seed":114006972768070745689169941537672783511558094441993283599713298597544575423459,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["Another command (pid=574752) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=594384) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=595475) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_prod_end': target 'otp_img_sigverify_always_prod_end' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.89883230973455074000772228234681395946478230382684547689460418934685684121248","seed":89883230973455074000772228234681395946478230382684547689460418934685684121248,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["Another command (pid=552127) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=551206) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=524804) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_always_rma': target 'otp_img_sigverify_always_rma' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.115132371841964691535828287304014458646269246865159490009081744683510283137047","seed":115132371841964691535828287304014458646269246865159490009081744683510283137047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=274488) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.78230104878309494684318110208663371305367367463964747579051414974043330073609","seed":78230104878309494684318110208663371305367367463964747579051414974043330073609,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=463076) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.54779250533504576432782848547543324815245965716889579794477547619336358023177","seed":54779250533504576432782848547543324815245965716889579794477547619336358023177,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["Another command (pid=478486) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=485601) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=490132) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.66452814469935500090343115760238758299006469827973444342361609766654908760536","seed":66452814469935500090343115760238758299006469827973444342361609766654908760536,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["Another command (pid=485290) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=488849) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=493069) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.57285747335751089262633014132094254074574760833305482123639779704325816201803","seed":57285747335751089262633014132094254074574760833305482123639779704325816201803,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["Another command (pid=506247) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=506524) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=366697) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.84752451066897653423069583187612657870619103029137692087397899637830575628039","seed":84752451066897653423069583187612657870619103029137692087397899637830575628039,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["Another command (pid=534228) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=539019) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=540272) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_test_unlocked0_exec_disabled': target 'img_test_unlocked0_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.27534600426702167809333091460138031889099165932798505605741000144755244143062","seed":27534600426702167809333091460138031889099165932798505605741000144755244143062,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["Another command (pid=522990) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=529943) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=530788) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.68582139242731383279032205444898475722590795319999284846656347311094998526836","seed":68582139242731383279032205444898475722590795319999284846656347311094998526836,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["Another command (pid=534228) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=539019) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=540272) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_rma_exec_disabled': target 'img_rma_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.8642380872420198554788422161215206834249008500295278547150206513208283410628","seed":8642380872420198554788422161215206834249008500295278547150206513208283410628,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["Another command (pid=367300) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=444016) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=442348) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.19867171918685557220116616120299629944028058875941698571673425300736408943261","seed":19867171918685557220116616120299629944028058875941698571673425300736408943261,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["Another command (pid=380271) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=442826) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=445956) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.21008538698105163144144145697068562535006983997989483310980249813149681974848","seed":21008538698105163144144145697068562535006983997989483310980249813149681974848,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["Another command (pid=365144) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=366143) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=367300) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:img_dev_exec_disabled': target 'img_dev_exec_disabled' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_static_critical","qual_name":"0.rom_e2e_static_critical.11877404260502264282762167948481803636336924943030236846207958159256537736126","seed":11877404260502264282762167948481803636336924943030236846207958159256537736126,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=601862) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=605961) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom:rom_with_fake_keys_sim_dv': target 'rom_with_fake_keys_sim_dv' not declared in package 'sw/device/silicon_creator/rom' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.43400053838613924480050759343970216902350849115713477477701143300470795525881","seed":43400053838613924480050759343970216902350849115713477477701143300470795525881,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["Another command (pid=526750) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=535662) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=534228) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.95926155492511599174575756235138140310866172011194698588835253177069639317908","seed":95926155492511599174575756235138140310866172011194698588835253177069639317908,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=529943) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_invalid_meas.83631673374791421459740852654137209866191933608242556630738421167933575702784","seed":83631673374791421459740852654137209866191933608242556630738421167933575702784,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["Another command (pid=589268) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=568373) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=562465) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.107460412444465286052447177769468901522842235347791468372302114145703608117291","seed":107460412444465286052447177769468901522842235347791468372302114145703608117291,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log","log_context":["Another command (pid=313436) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=280311) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=347658) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_test_unlocked0_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.108958083352174602555714666482876357774950382097873643284588170090750746301795","seed":108958083352174602555714666482876357774950382097873643284588170090750746301795,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=274488) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_otbn.40241394552089010176724737864314343818332455904130004782762113494667164422702","seed":40241394552089010176724737864314343818332455904130004782762113494667164422702,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_otbn/latest/run.log","log_context":["Another command (pid=576144) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=524804) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=576447) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_dev_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_dev_sw.85348227979362452035423649443976841160378136504135244472114402112440380434265","seed":85348227979362452035423649443976841160378136504135244472114402112440380434265,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_dev_sw/latest/run.log","log_context":["Another command (pid=551206) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=576144) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=524804) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_otbn.8016532996227480789684715820575552398367671927204892516806452077871479875161","seed":8016532996227480789684715820575552398367671927204892516806452077871479875161,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_otbn/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=595475) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=596334) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_sw.82547294605832566719694571448810519172242816810776357649033262582291912864716","seed":82547294605832566719694571448810519172242816810776357649033262582291912864716,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_sw/latest/run.log","log_context":["Another command (pid=598547) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=602305) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=604754) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_otbn.233770554543409015983992272886928301812070014215726611067120845338822754392","seed":233770554543409015983992272886928301812070014215726611067120845338822754392,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_otbn/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=524804) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=584832) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_prod_end_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_prod_end_sw.87550762374964123759118889763234843694014701681929936374495879887504291363025","seed":87550762374964123759118889763234843694014701681929936374495879887504291363025,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_prod_end_sw/latest/run.log","log_context":["Another command (pid=598547) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=602305) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=604754) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_otbn","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_otbn.55224668999709228109830841078089002069502347413069874798573137565041954201987","seed":55224668999709228109830841078089002069502347413069874798573137565041954201987,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_otbn/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=595475) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_sigverify_mod_exp_rma_sw","qual_name":"0.rom_e2e_sigverify_mod_exp_rma_sw.65075741633469797481248571350962858025941414678772551494339514202416792291217","seed":65075741633469797481248571350962858025941414678772551494339514202416792291217,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_rma_sw/latest/run.log","log_context":["Another command (pid=598547) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=602305) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=604754) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.26395969634271575487542517834294935932873333238319588170832731342021183846539","seed":26395969634271575487542517834294935932873333238319588170832731342021183846539,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=301350) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=313436) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=289374) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.54310800796560747412811236328057529991417418593619172223269799556513260315989","seed":54310800796560747412811236328057529991417418593619172223269799556513260315989,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=274488) is running. Waiting for it to complete on the server (server_pid=200843)...\n","Another command (pid=330997) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.77396228325495601311086807926755018225492139419161007879351384667015937865740","seed":77396228325495601311086807926755018225492139419161007879351384667015937865740,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=313436) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:otp_img_sigverify_mod_exp_rma_otbn': target 'otp_img_sigverify_mod_exp_rma_otbn' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_uart_smoketest_signed","qual_name":"0.chip_sw_uart_smoketest_signed.84568356041813207768265595709693630274001616291378370021092359499657857034094","seed":84568356041813207768265595709693630274001616291378370021092359499657857034094,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_smoketest_signed/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=460575) is running. Waiting for it to complete on the server (server_pid=200843)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:uart_smoketest_signed_sim_dv': no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:uart_smoketest_signed_sim_dv': target 'uart_smoketest_signed_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.109283752256904014292547129485550312520127210826110197665765866594273779377712","seed":109283752256904014292547129485550312520127210826110197665765866594273779377712,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["Use --verbose_failures to see the command lines of failed build steps.\n","ERROR: Analysis of target '//sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv' failed; build aborted: Target //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv is incompatible and cannot be built, but was explicitly requested.\n","Dependency chain:\n","    //sw/device/silicon_creator/lib/drivers:keymgr_functest_sim_dv (f2055d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible\n","INFO: Elapsed time: 0.249s, Critical Path: 0.03s\n","INFO: 1 process: 1 internal.\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_all_escalation_resets","qual_name":"0.chip_sw_all_escalation_resets.103902043808892021751952120012950264875935790975741613025385162733874715105278","seed":103902043808892021751952120012950264875935790975741613025385162733874715105278,"line":357,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 943.774000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.30078943109352909163739842060934018928449194643177752559532445485257680161000","seed":30078943109352909163739842060934018928449194643177752559532445485257680161000,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.12306863214005300754084463605792580129512197467991052755643468295092665979993","seed":12306863214005300754084463605792580129512197467991052755643468295092665979993,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 267.930000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.65674498145640905956170516747649545945115313108253062798607123927390975588647","seed":65674498145640905956170516747649545945115313108253062798607123927390975588647,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 177.040000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 177.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_lc_ctrl_rma_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rma_to_scrap.53453223479845029123668811669285733051149364605359738250215171573625649081236","seed":53453223479845029123668811669285733051149364605359738250215171573625649081236,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 171.672000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 171.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_raw_to_scrap","qual_name":"0.chip_sw_lc_ctrl_raw_to_scrap.59122912505001689115113960187644902891961922982532038465465570976537458113943","seed":59122912505001689115113960187644902891961922982532038465465570976537458113943,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 172.456000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 172.456000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_test_locked0_to_scrap","qual_name":"0.chip_sw_lc_ctrl_test_locked0_to_scrap.16822792648606968678748771772098661043107912288009182596492170993583950361308","seed":16822792648606968678748771772098661043107912288009182596492170993583950361308,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 174.696000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 174.696000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"0.chip_sw_lc_ctrl_rand_to_scrap.86832487913227723050808672480940299295850349276386940861922696084819953141103","seed":86832487913227723050808672480940299295850349276386940861922696084819953141103,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_ERROR @ 173.512000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 173.512000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.85140374599630714650961119810514851546272907027992407652946060608721626813350","seed":85140374599630714650961119810514851546272907027992407652946060608721626813350,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_ERROR @ 362.824000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 362.824000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.37102360870485404042453486306897877319370571531533586931472283803599920137987","seed":37102360870485404042453486306897877319370571531533586931472283803599920137987,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["UVM_ERROR @ 589.880000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 589.880000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.91039711920469387298089665122907001633836309926359593548582375515384995277015","seed":91039711920469387298089665122907001633836309926359593548582375515384995277015,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 118.488000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.488000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_rom_ctrl_integrity_check","qual_name":"0.chip_sw_rom_ctrl_integrity_check.110643183655074003026727218257518983803644391036995790922930501511023236820446","seed":110643183655074003026727218257518983803644391036995790922930501511023236820446,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/run.log","log_context":["UVM_ERROR @ 157.256000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 157.256000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_prim_tl_access","qual_name":"0.chip_prim_tl_access.45102502092825127239105998508442453898100163533952721691803006605665296931132","seed":45102502092825127239105998508442453898100163533952721691803006605665296931132,"line":234,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log","log_context":["UVM_ERROR @ 118.024000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 118.024000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.15965983266578936467541423407384291581550437797056454246411211663878078824195","seed":15965983266578936467541423407384291581550437797056454246411211663878078824195,"line":211,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_ERROR @ 120.728000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 120.728000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/lib/testing/alert_handler_testutils.c:78)] CHECK-fail: word_index < dump_size":[{"name":"chip_sw_rstmgr_alert_info","qual_name":"0.chip_sw_rstmgr_alert_info.27072584878402524787991191470744643130780833197601061429345329135823554279380","seed":27072584878402524787991191470744643130780833197601061429345329135823554279380,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log","log_context":["UVM_INFO @ 331.169000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((!rstreqs[*]) && (reset_cause != HwReq))'":[{"name":"chip_sw_rstmgr_cpu_info","qual_name":"0.chip_sw_rstmgr_cpu_info.67532823814304458274639550056693211346327707006444554546640565768917195379256","seed":67532823814304458274639550056693211346327707006444554546640565768917195379256,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log","log_context":["UVM_ERROR @ 412.016000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 412.016000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_aes_trans","qual_name":"0.chip_sw_clkmgr_off_aes_trans.104223996505385824839754397897909815346641339798493093645311071797471464944256","seed":104223996505385824839754397897909815346641339798493093645311071797471464944256,"line":323,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log","log_context":["UVM_ERROR @ 185.328000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_hmac_trans","qual_name":"0.chip_sw_clkmgr_off_hmac_trans.43751610614555400609326306336846705238010498849181486339172529021951492141218","seed":43751610614555400609326306336846705238010498849181486339172529021951492141218,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.280000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_kmac_trans","qual_name":"0.chip_sw_clkmgr_off_kmac_trans.47694078298888595944572782288551736063941022556926101835112589025494114781898","seed":47694078298888595944572782288551736063941022556926101835112589025494114781898,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log","log_context":["UVM_ERROR @ 185.312000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_clkmgr_off_otbn_trans","qual_name":"0.chip_sw_clkmgr_off_otbn_trans.55739674070039108382959268372127322274655207704691899657153927444099776953576","seed":55739674070039108382959268372127322274655207704691899657153927444099776953576,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log","log_context":["UVM_ERROR @ 185.184000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A\n","UVM_INFO @ 185.184000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!":[{"name":"chip_sw_soc_proxy_smoketest","qual_name":"0.chip_sw_soc_proxy_smoketest.4771882571294469031914059064647647951886238852156101570012791043181977971427","seed":4771882571294469031914059064647647951886238852156101570012791043181977971427,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log","log_context":["UVM_INFO @ 156.160000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns *":[{"name":"chip_sw_soc_proxy_external_wakeup","qual_name":"0.chip_sw_soc_proxy_external_wakeup.30238905304423576251170328143571885282068516413872377686168498828256332046526","seed":30238905304423576251170328143571885282068516413872377686168498828256332046526,"line":324,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log","log_context":["UVM_INFO @ 157.829000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec":[{"name":"chip_sw_aon_timer_irq","qual_name":"0.chip_sw_aon_timer_irq.114171642245788566980424993158495123823406515924191880934717023457556616015461","seed":114171642245788566980424993158495123823406515924191880934717023457556616015461,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log","log_context":["UVM_INFO @ 483.292000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds":[{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.274462385754096743524434177518073570117988902507880803627936542322529294297","seed":274462385754096743524434177518073570117988902507880803627936542322529294297,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_INFO @ 182.403000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (dv_utils_pkg.sv:267) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from \"kJitterEnabled.dat\"":[{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en.45447511705056513801808287969108354031599550767389634766954182936599260735919","seed":45447511705056513801808287969108354031599550767389634766954182936599260735919,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en","qual_name":"0.chip_sw_aes_enc_jitter_en.38071376538058207905378214773169847520637365401703209848337294295441917189940","seed":38071376538058207905378214773169847520637365401703209848337294295441917189940,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en","qual_name":"0.chip_sw_hmac_enc_jitter_en.54234608831079623748647113841235508483738551741805849297871332511999642681626","seed":54234608831079623748647113841235508483738551741805849297871332511999642681626,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en.101214465709643640126551532340144087237128495986524063847700136902026606349434","seed":101214465709643640126551532340144087237128495986524063847700136902026606349434,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en.103225255465064690903261491593778859305546574358333130555907250306374327896988","seed":103225255465064690903261491593778859305546574358333130555907250306374327896988,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log","log_context":["UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq","qual_name":"0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.41478826017066270092181945789235575585578274640352917598196346610561076562901","seed":41478826017066270092181945789235575585578274640352917598196346610561076562901,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_aes_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_aes_enc_jitter_en_reduced_freq.32484529773815407997170943023605366470513422706733378285073212963605237315486","seed":32484529773815407997170943023605366470513422706733378285073212963605237315486,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_hmac_enc_jitter_en_reduced_freq","qual_name":"0.chip_sw_hmac_enc_jitter_en_reduced_freq.56638394997078579304545142290000669230171182707149616659818024336680652828866","seed":56638394997078579304545142290000669230171182707149616659818024336680652828866,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.27509190062077816276983413623204837563613789209500619882929646995890515909830","seed":27509190062077816276983413623204837563613789209500619882929646995890515909830,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq","qual_name":"0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.21909594483861611056018960487046949978607833481899270620596934973300781868701","seed":21909594483861611056018960487046949978607833481899270620596934973300781868701,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq","qual_name":"0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.73960040062050064083836233552844845306756856885661597764730038434657369465312","seed":73960040062050064083836233552844845306756856885661597764730038434657369465312,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"0.chip_sw_csrng_edn_concurrency_reduced_freq.48257298068128407073700141847213481446904935471368646925425969648530402738610","seed":48257298068128407073700141847213481446904935471368646925425969648530402738610,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired":[{"name":"chip_sw_rv_core_ibex_nmi_irq","qual_name":"0.chip_sw_rv_core_ibex_nmi_irq.77817016808564795020627782357258533778299589746193332296540381889377010719271","seed":77817016808564795020627782357258533778299589746193332296540381889377010719271,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log","log_context":["UVM_INFO @ 269.308000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP":[{"name":"chip_sw_keymgr_dpe_key_derivation","qual_name":"0.chip_sw_keymgr_dpe_key_derivation.2690888626532937670471337772427576768923409753737405588133861042660716679582","seed":2690888626532937670471337772427576768923409753737405588133861042660716679582,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log","log_context":["UVM_INFO @ 304.762000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_keymgr_dpe_key_derivation_prod","qual_name":"0.chip_sw_keymgr_dpe_key_derivation_prod.63809307708878214748049692028431291910964032441797045578868379916114202414989","seed":63809307708878214748049692028431291910964032441797045578868379916114202414989,"line":340,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log","log_context":["UVM_INFO @ 304.833000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)'":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.40697020971739109664410078528823662772848808813165795536004829268803719722235","seed":40697020971739109664410078528823662772848808813165795536004829268803719722235,"line":232,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":["UVM_ERROR @ 118.019000 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange\n","UVM_INFO @ 118.019000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (jtag_riscv_driver.sv:221) [jtag_riscv_agent_pkg] Check failed sbcs_val[SbAccess32] == * (* [*] vs * [*]) expect SBA width to be * bits!":[{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.4506995910826383035781058382059804173404503433294059006094191676779804342463","seed":4506995910826383035781058382059804173404503433294059006094191676779804342463,"line":5956,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 132.035000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.4143826653874797955594773454992887666981977644810851217230972649598239651230","seed":4143826653874797955594773454992887666981977644810851217230972649598239651230,"line":5956,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 131.238000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[CNST-CIF] Constraints inconsistency failure":[{"name":"chip_padctrl_attributes","qual_name":"0.chip_padctrl_attributes.43952381172381815654536681344633625432689421211485464816010678919837600623529","seed":43952381172381815654536681344633625432689421211485464816010678919837600623529,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log","log_context":["src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 143\n","  Constraints are inconsistent and cannot be solved.\n","  Please check the inconsistent constraints being printed above and rewrite \n","  them.\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == *":[{"name":"chip_sw_dma_abort","qual_name":"0.chip_sw_dma_abort.39885418233543721589149526713352944669776325237393781552121224112106734416611","seed":39885418233543721589149526713352944669776325237393781552121224112106734416611,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log","log_context":["UVM_INFO @ 211.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":75,"total":242,"percent":30.99173553719008}