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resolved to a hdl object (vlog,vhdl,vlog-slice)\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.4761766530685785427143864928457184404277341548492845968987539238359181403347","seed":4761766530685785427143864928457184404277341548492845968987539238359181403347,"line":85,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-xcelium/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1339007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc2cab [110011000010110010101011] vs 0x0 [0]) \n","UVM_ERROR @   1356007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaf65f0 [101011110110010111110000] vs 0x0 [0]) \n","UVM_ERROR @   1370007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97487a [100101110100100001111010] vs 0x0 [0]) \n","UVM_ERROR @   1427007 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b34b [101011001101001011] vs 0x0 [0]) \n"]}]}},"passed":31,"total":33,"percent":93.93939393939394}