{"block":{"name":"dma","variant":null,"commit":"b583fba84cfd9603694abab6a1f8e97cf2cfcd19","commit_short":"b583fba","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/b583fba84cfd9603694abab6a1f8e97cf2cfcd19","revision_info":"GitHub Revision: [`b583fba`](https://github.com/lowrisc/opentitan/tree/b583fba84cfd9603694abab6a1f8e97cf2cfcd19)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-07-21T19:39:46Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/dma/data/dma_testplan.html","stages":{"V1":{"testpoints":{"dma_memory_smoke":{"tests":{"dma_memory_smoke":{"max_time":5.0,"sim_time":1294.205283,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_smoke":{"tests":{"dma_handshake_smoke":{"max_time":6.0,"sim_time":292.189739,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_generic_smoke":{"tests":{"dma_generic_smoke":{"max_time":5.0,"sim_time":313.172125,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":30.162826000000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"dma_csr_rw":{"max_time":1.0,"sim_time":47.43182100000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"dma_csr_bit_bash":{"max_time":6.0,"sim_time":5701.593399,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"dma_csr_aliasing":{"max_time":4.0,"sim_time":260.76207800000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"dma_csr_mem_rw_with_rand_reset":{"max_time":1.0,"sim_time":55.221394999999994,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"dma_csr_rw":{"max_time":1.0,"sim_time":47.43182100000001,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":4.0,"sim_time":260.76207800000003,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"V2":{"testpoints":{"dma_memory_region_lock":{"tests":{"dma_memory_region_lock":{"max_time":46.0,"sim_time":15450.585617,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_memory_tl_error":{"tests":{"dma_memory_stress":{"max_time":200.0,"sim_time":16322.743939999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_tl_error":{"tests":{"dma_handshake_stress":{"max_time":625.0,"sim_time":218517.629486,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_stress":{"tests":{"dma_handshake_stress":{"max_time":625.0,"sim_time":218517.629486,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_memory_stress":{"tests":{"dma_memory_stress":{"max_time":200.0,"sim_time":16322.743939999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_generic_stress":{"tests":{"dma_generic_stress":{"max_time":621.0,"sim_time":196723.545263,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_handshake_mem_buffer_overflow":{"tests":{"dma_handshake_stress":{"max_time":625.0,"sim_time":218517.629486,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_abort":{"tests":{"dma_abort":{"max_time":10.0,"sim_time":2813.223434,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"dma_stress_all":{"tests":{"dma_stress_all":{"max_time":315.0,"sim_time":112264.43525,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"dma_alert_test":{"max_time":2.0,"sim_time":21.493588,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"dma_intr_test":{"max_time":1.0,"sim_time":20.292684,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"dma_tl_errors":{"max_time":2.0,"sim_time":25.51618,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"dma_tl_errors":{"max_time":2.0,"sim_time":25.51618,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":30.162826000000003,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":1.0,"sim_time":47.43182100000001,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":4.0,"sim_time":260.76207800000003,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":2.0,"sim_time":349.174825,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0},"tl_d_partial_access":{"tests":{"dma_csr_hw_reset":{"max_time":1.0,"sim_time":30.162826000000003,"passed":1,"total":1,"percent":100.0},"dma_csr_rw":{"max_time":1.0,"sim_time":47.43182100000001,"passed":1,"total":1,"percent":100.0},"dma_csr_aliasing":{"max_time":4.0,"sim_time":260.76207800000003,"passed":1,"total":1,"percent":100.0},"dma_same_csr_outstanding":{"max_time":2.0,"sim_time":349.174825,"passed":1,"total":1,"percent":100.0}},"passed":4,"total":4,"percent":100.0}},"passed":13,"total":13,"percent":100.0},"V2S":{"testpoints":{"dma_illegal_addr_range":{"tests":{"dma_mem_enabled":{"max_time":19.0,"sim_time":435.964676,"passed":1,"total":1,"percent":100.0},"dma_generic_stress":{"max_time":621.0,"sim_time":196723.545263,"passed":1,"total":1,"percent":100.0},"dma_handshake_stress":{"max_time":625.0,"sim_time":218517.629486,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"dma_config_lock":{"tests":{"dma_config_lock":{"max_time":5.0,"sim_time":303.76261999999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_intg_err":{"tests":{"dma_tl_intg_err":{"max_time":4.0,"sim_time":200.851656,"passed":1,"total":1,"percent":100.0},"dma_sec_cm":{"max_time":2.0,"sim_time":59.010351,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"dma_short_transfer":{"max_time":63.0,"sim_time":16445.410998,"passed":1,"total":1,"percent":100.0},"dma_longer_transfer":{"max_time":9.0,"sim_time":87.750807,"passed":1,"total":1,"percent":100.0},"dma_stress_all_with_rand_reset":{"max_time":6.0,"sim_time":255.26777600000003,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667}},"coverage":{"code":{"block":97.34,"line_statement":96.85,"branch":95.76,"condition_expression":null,"toggle":77.37,"fsm":91.55},"assertion":96.61,"functional":63.85},"cov_report_page":"/nightly/current_run/scratch/master/dma-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"dma_stress_all_with_rand_reset","qual_name":"0.dma_stress_all_with_rand_reset.45494866730772316311514161758355843051552675216105617351227524317373508863847","seed":45494866730772316311514161758355843051552675216105617351227524317373508863847,"line":106,"log_path":"/nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  255267776ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":24,"total":25,"percent":96.0}