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(uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_long_xfer_wo_dly","qual_name":"0.uart_long_xfer_wo_dly.69119587699705062452018417871639101325078740606905780517835257076348191696100","seed":69119587699705062452018417871639101325078740606905780517835257076348191696100,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_long_xfer_wo_dly/latest/run.log","log_context":["UVM_ERROR @ 71500973118 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 74549115150 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_INFO @ 76145480862 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/5\n","UVM_INFO @ 80669634662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}],"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.42384542217367730898401552707458232036723318449553357307396995957449189704606","seed":42384542217367730898401552707458232036723318449553357307396995957449189704606,"line":191,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15767746057 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 15837871057 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/369\n","UVM_INFO @ 16197558557 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/369\n","UVM_INFO @ 16390683557 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/369\n"]},{"name":"uart_stress_all","qual_name":"0.uart_stress_all.58876924892539600945592172676667458676862991591321249448839899420183509895063","seed":58876924892539600945592172676667458676862991591321249448839899420183509895063,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 10313900406 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10474666398 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 10474705614 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10474764438 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n"]}]}},"passed":24,"total":27,"percent":88.88888888888889}