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otp_ctrl_core_reg_block.err_code_*":[{"name":"otp_ctrl_parallel_lc_esc","qual_name":"0.otp_ctrl_parallel_lc_esc.94718719207186930259148257034248415250035628106798073231428317184960920840398","seed":94718719207186930259148257034248415250035628106798073231428317184960920840398,"line":1088,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest/run.log","log_context":["UVM_INFO @  90801877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_check_fail","qual_name":"0.otp_ctrl_check_fail.57898326341144975032987703719832928138833739077880186286563483629005517907154","seed":57898326341144975032987703719832928138833739077880186286563483629005517907154,"line":2440,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest/run.log","log_context":["UVM_INFO @ 169517906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.103667272272182419998512468479605470826765409816092981108387140817873880760166","seed":103667272272182419998512468479605470826765409816092981108387140817873880760166,"line":2714,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1101423333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *":[{"name":"otp_ctrl_regwen","qual_name":"0.otp_ctrl_regwen.30861134737216605581347120319101347346274242549955144549892464958967535601662","seed":30861134737216605581347120319101347346274242549955144549892464958967535601662,"line":3402,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest/run.log","log_context":["UVM_INFO @ 620655851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state":[{"name":"otp_ctrl_stress_all","qual_name":"0.otp_ctrl_stress_all.68119577161866480273298944516015416907616425468232892524057054611106990255434","seed":68119577161866480273298944516015416907616425468232892524057054611106990255434,"line":12671,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 1426492764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"otp_ctrl_sec_cm","qual_name":"0.otp_ctrl_sec_cm.7256713947154844495002005320339902356010707010270280947739489481743547623165","seed":7256713947154844495002005320339902356010707010270280947739489481743547623165,"line":2691,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest/run.log","log_context":["UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":19,"total":30,"percent":63.333333333333336}