{"block":{"name":"uart","variant":null,"commit":"377160a7ea64bf6b187127db5f2bc6819b7ff196","commit_short":"377160a","dirty":true,"branch":"master","url":"https://github.com/lowRISC/opentitan/tree/377160a7ea64bf6b187127db5f2bc6819b7ff196","revision_info":"GitHub Revision: [`377160a`](https://github.com/lowrisc/opentitan/tree/377160a7ea64bf6b187127db5f2bc6819b7ff196)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-08-06T19:53:31Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":2.0,"sim_time":290.68186599999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":1130.2612720000002,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":1.0,"sim_time":27.050167000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.0,"sim_time":651.342295,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.0,"sim_time":79.37786,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":21.541241000000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":1.0,"sim_time":27.050167000000002,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":79.37786,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0}},"passed":5,"total":6,"percent":83.33333333333333},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":8.0,"sim_time":19531.13152,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":2.0,"sim_time":290.68186599999996,"passed":1,"total":1,"percent":100.0},"uart_tx_rx":{"max_time":8.0,"sim_time":19531.13152,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":101.0,"sim_time":342788.617995,"passed":1,"total":1,"percent":100.0},"uart_rx_parity_err":{"max_time":114.0,"sim_time":114999.011465,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":8.0,"sim_time":19531.13152,"passed":1,"total":1,"percent":100.0},"uart_intr":{"max_time":101.0,"sim_time":342788.617995,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":37.0,"sim_time":147970.693544,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":84.0,"sim_time":74083.388221,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":33.0,"sim_time":19906.516303,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":101.0,"sim_time":342788.617995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":101.0,"sim_time":342788.617995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":101.0,"sim_time":342788.617995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":136.0,"sim_time":12907.658718,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":3.0,"sim_time":2772.817729,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":3.0,"sim_time":2772.817729,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":19.0,"sim_time":159995.348472,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":17.0,"sim_time":57687.755704999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":3.0,"sim_time":568.809184,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":30.0,"sim_time":5682.601925,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":147.0,"sim_time":166053.573588,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":83.0,"sim_time":404038.438579,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":1.0,"sim_time":21.947615000000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":1.0,"sim_time":89.565128,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.0,"sim_time":334.39148800000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.0,"sim_time":334.39148800000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":1130.2612720000002,"passed":0,"total":1,"percent":0.0},"uart_csr_rw":{"max_time":1.0,"sim_time":27.050167000000002,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":79.37786,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.0,"sim_time":74.27922500000001,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":4,"percent":75.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.0,"sim_time":1130.2612720000002,"passed":0,"total":1,"percent":0.0},"uart_csr_rw":{"max_time":1.0,"sim_time":27.050167000000002,"passed":1,"total":1,"percent":100.0},"uart_csr_aliasing":{"max_time":1.0,"sim_time":79.37786,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.0,"sim_time":74.27922500000001,"passed":1,"total":1,"percent":100.0}},"passed":3,"total":4,"percent":75.0}},"passed":20,"total":22,"percent":90.9090909090909},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.0,"sim_time":142.906521,"passed":1,"total":1,"percent":100.0},"uart_tl_intg_err":{"max_time":1.0,"sim_time":74.222212,"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.0,"sim_time":74.222212,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":14.0,"sim_time":2744.1185240000004,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"coverage":{"code":{"block":98.41,"line_statement":98.95,"branch":96.87,"condition_expression":null,"toggle":73.08,"fsm":25.0},"assertion":98.85,"functional":90.69},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.63377896704648307172449357439379501419372548411298730084176011145984861860027","seed":63377896704648307172449357439379501419372548411298730084176011145984861860027,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 150680691120 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 150680913342 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 150682024452 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (180 [0xb4] vs 222 [0xde]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 150685357782 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"0.uart_stress_all_with_rand_reset.19977050738566544280319281716781639220820183028597219125995860936379567634470","seed":19977050738566544280319281716781639220820183028597219125995860936379567634470,"line":141,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2669119124 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2676425188 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2685118996 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2690220996 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_monitor.sv:187) monitor [monitor] Expect uart_tx stable from * to * of the period, but it's changed":[{"name":"uart_csr_hw_reset","qual_name":"0.uart_csr_hw_reset.94006394175794145156177301761095892516043519563579797132382322536227288595628","seed":94006394175794145156177301761095892516043519563579797132382322536227288595628,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_hw_reset/latest/run.log","log_context":["UVM_INFO @ 1042806809 ps: (dv_base_vseq.sv:191) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running csr hw_reset vseq iteration 2/2.\n","UVM_INFO @ 1130261272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":24,"total":27,"percent":88.88888888888889}