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*":[{"name":"otp_ctrl_parallel_lc_req","qual_name":"0.otp_ctrl_parallel_lc_req.74158117590859704688732351055719662022996124187854562287462623293134274921154","seed":74158117590859704688732351055719662022996124187854562287462623293134274921154,"line":8275,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest/run.log","log_context":["UVM_INFO @ 5562554490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_parallel_key_req","qual_name":"0.otp_ctrl_parallel_key_req.60706419376063947866575756720180710643991563113352749962843773076763888054774","seed":60706419376063947866575756720180710643991563113352749962843773076763888054774,"line":15535,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest/run.log","log_context":["UVM_INFO @ 472041736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.34971124751723537339742929397175061685281754637077253315796516040143754124488","seed":34971124751723537339742929397175061685281754637077253315796516040143754124488,"line":10218,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 795487338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred!":[{"name":"otp_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.otp_ctrl_csr_mem_rw_with_rand_reset.84381344196806715011646303867374277075937543819190747932315062599410970084625","seed":84381344196806715011646303867374277075937543819190747932315062599410970084625,"line":107,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10217043781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":21,"total":30,"percent":70.0}