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---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*":[{"name":"otp_ctrl_dai_errs","qual_name":"0.otp_ctrl_dai_errs.57093690213206008621757044359112142260137075471721177788445334941667283135371","seed":57093690213206008621757044359112142260137075471721177788445334941667283135371,"line":2734,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log","log_context":["UVM_INFO @ 1232390253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *":[{"name":"otp_ctrl_regwen","qual_name":"0.otp_ctrl_regwen.11704688799125839603712670601495908764235947363143267232094503731809797942655","seed":11704688799125839603712670601495908764235947363143267232094503731809797942655,"line":9466,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest/run.log","log_context":["UVM_INFO @ 1239680963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr":[{"name":"otp_ctrl_test_access","qual_name":"0.otp_ctrl_test_access.39578317811200642198600480487641229857128026911994594061266761444702569407319","seed":39578317811200642198600480487641229857128026911994594061266761444702569407319,"line":6345,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest/run.log","log_context":["UVM_INFO @ 569406021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.34412571467236412348419302661632657970165711241613783372731307985138454657910","seed":34412571467236412348419302661632657970165711241613783372731307985138454657910,"line":887,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 316496045 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1\n","UVM_INFO @ 316568964 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1\n","UVM_INFO @ 316850223 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1\n","UVM_INFO @ 316902308 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *":[{"name":"otp_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.otp_ctrl_csr_mem_rw_with_rand_reset.14127723075099105607294323591128911411323919226277044997328208914978367732593","seed":14127723075099105607294323591128911411323919226277044997328208914978367732593,"line":97,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  48726615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":20,"total":30,"percent":66.66666666666667}