{"block":{"name":"clkmgr","variant":null,"commit":"4e5c99db524e99425cb78ca6f2714e5287fa800c","commit_short":"4e5c99d","dirty":true,"branch":"master","url":"https://github.com/lowRISC/opentitan/tree/4e5c99db524e99425cb78ca6f2714e5287fa800c","revision_info":"GitHub Revision: [`4e5c99d`](https://github.com/lowrisc/opentitan/tree/4e5c99db524e99425cb78ca6f2714e5287fa800c)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-01T21:34:42Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":1.61,"sim_time":76.626895,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.14,"sim_time":17.383168,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":3.39,"sim_time":194.01814000000002,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":0.99,"sim_time":2.948525,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.49,"sim_time":33.516055,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.99,"sim_time":2.948525,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.47,"sim_time":36.214048999999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":3.26,"sim_time":226.78124400000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":0.84,"sim_time":24.185446,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":1.61,"sim_time":76.626895,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":6.390383,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.85,"sim_time":4.093572,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":6.390383,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":2.12,"sim_time":87.88519500000001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.15,"sim_time":19.325467,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":4.42,"sim_time":220.48083799999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":4.42,"sim_time":220.48083799999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.14,"sim_time":17.383168,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.99,"sim_time":2.948525,"passed":0,"total":1,"percent":0.0},"clkmgr_same_csr_outstanding":{"max_time":1.0,"sim_time":3.827775,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":4,"percent":25.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.14,"sim_time":17.383168,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":0.99,"sim_time":2.948525,"passed":0,"total":1,"percent":0.0},"clkmgr_same_csr_outstanding":{"max_time":1.0,"sim_time":3.827775,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":4,"percent":25.0}},"passed":7,"total":13,"percent":53.84615384615385},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":3.49,"sim_time":268.392597,"passed":1,"total":1,"percent":100.0},"clkmgr_tl_intg_err":{"max_time":1.28,"sim_time":20.543557,"passed":0,"total":1,"percent":0.0}},"passed":1,"total":2,"percent":50.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.53,"sim_time":62.927980000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.53,"sim_time":62.927980000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.53,"sim_time":62.927980000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.53,"sim_time":62.927980000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":0.98,"sim_time":18.358565,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":1.28,"sim_time":20.543557,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":0.98,"sim_time":6.390383,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.85,"sim_time":4.093572,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.53,"sim_time":62.927980000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":3.96,"sim_time":389.022994,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":3.49,"sim_time":268.392597,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.78,"sim_time":3.740059,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":3.49,"sim_time":268.392597,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":3,"total":8,"percent":37.5},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":1.16,"sim_time":28.431643,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":2.53,"sim_time":31.132633000000002,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":82.32,"branch":87.53,"condition_expression":79.45,"toggle":98.87,"fsm":0.0},"assertion":90.08,"functional":71.54},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.87718499868761331537473795405238516701524817220753466235218330785384608185753","seed":87718499868761331537473795405238516701524817220753466235218330785384608185753,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_INFO @   6390383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.76818170973425982702798937210896985394134386123264002097242001128958081437408","seed":76818170973425982702798937210896985394134386123264002097242001128958081437408,"line":157,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_INFO @  87885195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.63053281047240149760048480423122771785856008276603298091482624471761905685806","seed":63053281047240149760048480423122771785856008276603298091482624471761905685806,"line":84,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_INFO @   4093572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.17530117299894464677136071597214725700631383930423004820633917215335061762792","seed":17530117299894464677136071597214725700631383930423004820633917215335061762792,"line":137,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  31132633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.98846432012337411620416099809777518777719152347467333333533718907770542591711","seed":98846432012337411620416099809777518777719152347467333333533718907770542591711,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_INFO @  28431643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.9588698071731419785435685417810430037628260000557984970129535542842933695565","seed":9588698071731419785435685417810430037628260000557984970129535542842933695565,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_INFO @  18358565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.30607282983993811367829188239114795259537815615093756392284053845013126793819","seed":30607282983993811367829188239114795259537815615093756392284053845013126793819,"line":102,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_INFO @  20543557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"0.clkmgr_csr_rw.1876279440351397077367670259937809738842268642701752490719252146680997462758","seed":1876279440351397077367670259937809738842268642701752490719252146680997462758,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log","log_context":["UVM_INFO @   3740059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.31508268024869158132123537217651820696934450211512001999570525353026083610921","seed":31508268024869158132123537217651820696934450211512001999570525353026083610921,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @ 194018140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_csr_aliasing","qual_name":"0.clkmgr_csr_aliasing.71836834876934061796759464596999689829115350457457109844895819803013786352987","seed":71836834876934061796759464596999689829115350457457109844895819803013786352987,"line":87,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest/run.log","log_context":["UVM_INFO @   2948525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.68468479724498895062891792079835209860895166229312249041799699939563449813424","seed":68468479724498895062891792079835209860895166229312249041799699939563449813424,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @   3827775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":11,"total":22,"percent":50.0}